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This chapter of the book is not intended as a comprehensive VHDL reference book as there are many excellent texts available that fit that purpose, including Zwolinski [1], Navabi [2], or Ashenden [3] (full details are provided in the References heading).
Instead, this chapter is designed to give concise and useful summary information on important language constructs and usage in VHDL, hopefully helpful and easy to use, but not necessarily comprehensive. The information is helpful enough for the reader to understand the key concepts in this book; however, I would thoroughly recommend obtaining access to a textbook on VHDL or Verilog if the reader is serious in becoming expert in HDL design for digital systems. This book is intended as a complement to a textbook.
This chapter will introduce the key concepts in VHDL and the important syntax required for most VHDL designs, particularly with reference to FPGAs. In most cases, the decision to use VHDL over other languages such as Verilog or SystemC will have less to do with designer choice and more to do with software availability and company decisions. Over the last decade or so, a war of words has raged between the VHDL and Verilog communities about which is the best language, and in most cases it is completely pointless as the issue is more about design than syntax. There are numerous differences in the details between VHDL and Verilog, but the fundamental philosophical difference historically has been the design context of the two languages.
Verilog has come from a bottom-up tradition and has been heavily used by the IC industry for cell-based design, whereas the VHDL language has been developed much more from a top-down perspective. Of course, these are generalizations and largely out of date in a modern context, but the result is clearly seen in the basic syntax and methods of the two languages. While this has possibly been the case in the past, with the advent of the higher level “SystemVerilog” variant of Verilog providing much of the same capability as VHDL at the system level, this has also become popular.
Unfortunately, while there are many languages now available to designers, most of the FPGA design tools support subsets, and therefore in some cases support for SystemVerilog may be
patchy. It is therefore useful to describe using VHDL and Verilog; however, this book will also provide some introductory material to SystemVerilog for completeness.
Without descending into a minute dissection of the differences between Verilog and VHDL, one important aspect of VHDL is the ability to use multiple levels of model with different architectures as shown in Figure 3.1.
This is not unique to VHDL, and in fact Verilog does have the concept of different behavior in a single module; however, it is explicitly defined in VHDL and is extremely useful in putting together practical multi-level designs in VHDL. The division of a model into its interface part (the entity in VHDL) and the behavior part (the architecture in VHDL) is an incredibly practical approach for modeling multiple behavior for a single interface and makes model exchange and multiple implementation practical.
The remainder of this chapter will describe the key parts of VHDL, starting with the definition of a basic model structure using entities and architectures, discuss the important variable types, review the methods of encapsulating concurrent, sequential and hierarchical behavior and finally introduce the important fundamental data types required in VHDL.
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