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Home > FPGA Technical Tutorials > The Zynq Book Tutorials > Next Steps in Zynq SoC Design

Next Steps in Zynq SoC Design

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Introduction

This tutorial will guide you through the process of creating a Zynq design utilising interrupts. Using the Vivado™ Integraded Development Environment (IDE) and the IP Integrator environment, a simple Zynq™ processor design, to be implemented on the ZedBoard, will be generated. The Software Development Kit (SDK) will then be used to create a simple software application which will run on the Zynq’s ARM Processing System (PS) to control the hardware that is implemented in the Programmable Logic (PL). This tutorial leads on from the previous one, expanding on the skills acquired in it.

The tutorial is split into four exercises, and is organised as follows:

Exercise 2A — This exercise provides a further guide to the process of launching Vivado IDE and creating a project using New Project Wizard

Exercise 2B — In this exercise, we will use the project that was created in Exercise 2A to build a Zynq embedded system utilising interrupts with IP Integrator and incorporating existing IP from the Vivado IP Catalog. This will expand on previous knowledge gained in creating and connecting a block based system in IP Integrator. The completed design will have an associated bitstream generated and will be exported to the Xilinx SDK for creating of a test application.

Exercise 2C — In the Xilinx SDK, a test software application for the generated hardware system will be created and explained. Running this application on the ZedBoard will demonstrate the function of interrupts and how the application is coded to utilise them.

Exercise 2D — Finally, we will return to the system from Exercise 2B and include an additional source of interrupt, making the necessary connections, and generating a bitstream and exporting to the Xilinx SDK. We will then modify our previous software application to inspect the operation of the altered system.



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