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Intellectual property ( IP ) cores are fundamental criteria when selecting which FPGA vendor and specifi c part to choose for a design. IP provides an easy mecha- nism for incorporating complex logic in your designs, from high-speed gigahertz transceivers (GTs) to digital signal processors (DSPs) as well as soft microproces- sors (MicroBlaze) to an embedded ARM system on a chip (SoC). Xilinx-provided IP have been optimized and tested to work with the FPGA resources including DPS, block RAM, and IO, greatly accelerating design development.
Most of the IP provided in the Vivado Design Suite have the license included, allowing the use of the IP in your designs. Some IP require a license to be purchased from Xilinx or an Alliance partner. IP licensing information is provided in the IP Catalog which will direct you to the appropriate web source.
The Vivado Design Suite includes the IP Catalog to deliver plug-and-play Xilinx IP as well as some third-party alliance partner IP. The catalog can be expanded with additional IP from third party IP developers or your own created IP. Your own IP could be created through:
• C/C++ algorithms compiled using the Vivado high-level synthesis ( HLS ) tool (see Chap. 10 )
• Modules from system generator for DSP designs (MATLAB ® from Simulink ® algorithms) (see Chap. 8 )
• Designs packaged as IP using the Vivado Design Suite IP Packager
The Vivado IP Packager enables you to create plug-and-play IP which can be added to the extensible Vivado IP Catalog. The IP Packager is based on IP-XACT (IEEE Standard 1685), Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows .
After you have assembled a Vivado Design Suite project, the IP Packager lets you turn your design into a reusable IP module that you can then add to the Vivado IP Catalog and that others can use as a design source.
The IP Catalog is available either from within a Vivado Design Suite project or using a special Managed IP project. Both are available from the start screen.
The overall fl ow for IP consists of the following stages:
• Use the IP Catalog to fi nd the IP required for the design.
• Customize the IP by specifying confi guration options (produces an IP custom- ization .xci).
• Generate the IP (Generate Output Products).
– Copy fi les from the Vivado Design Suite installation area to the user-specifi ed location or project.
– By default include synthesizing the IP stand-alone ( out-of-context ).
• Instantiate the IP in designs (or in an IP integrator block design).
• Simulate.
– Behavioral
– Netlist
• Synthesize and implement.
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