FONT SIZE : AAA
So far we have explored the tasks involved in porting an SoC design onto an FPGA equivalent form and how following some Design-for-Prototyping rules, these tasks can be made easier. A significant part of the porting effort will be put towards handling pre-existing intellectual property (IP), and particularly peripheral IP for interfaces in the design and so it is deserving of its own chapter. In this chapter we shall explore the two most popular groups of IP, namely CPU and interfaces and how we can model these in an FPGA-based prototype given that we may or may not have access to hard models, to RTL or even to an equivalent IP already available in FPGA-compatible form.
Manufacturer:Xilinx
Product Categories:
Lifecycle:Unconfirmed -
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Programmable logic array
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Programmable logic array
Lifecycle:Active Active
RoHS: No RoHS
Support
