TABLE OF CONTENTS

• Preface
• The challenge of system verification
  • Moore was right!
  • The economics of SoC design
  • Virtual platforms: prototyping without hardware
  • Prototyping use models
  • User priorities in prototyping
  • Chip design trends
  • Summary
• What can FPGA-based prototyping do for us?
  • FPGA-based prototyping for different aims
  • Interfacing benefit: test real-world data effects
  • Benefits for feasibility lab experiments
  • Prototype usage out of the lab
  • What can’t FPGA-based prototyping do for us?
  • Summary: So why use FPGA-based prototyping?
• FPGA technology today: chips and tools
  • FPGA device technology today
  • FPGA–based Prototyping process overview
  • Implementation tools needed during prototyping
  • Design partitioning flows
  • FPGA back-end (place & route) flow
  • Debugging tools
  • Summary
• Getting started
  • A getting-started checklist
  • Estimating the required resources: FPGAs
  • How many FPGAs can be used in one prototype?
  • Estimating required resources
  • How long will it take to process the design?
  • How much work will it be?
  • FPGA platform
  • Summary
• Which platform? (1) build-your-own
  • What is the best shape for the platform?
  • Testability
  • On-board clock resources
  • Clock control and configuration
  • On-board Voltage Domains
  • Power supply and distribution
  • System reliability management
  • FPGA configuration
  • Signal integrity
  • Global start-up and reset
  • Robustness
  • Adopting a standard in-house platform
• Which platform? (2) ready-made
  • What do you need the board to do?
  • Choosing the board(s) to meet your goals
  • Flexibility: modularity
  • Flexibility: interconnect
  • What is the ideal interconnect topology?
  • Speed: the effect of interconnect delay
  • Speed: quality of design and layout
  • On-board support for signal multiplexing
  • Cost and robustness
  • Capacity
  • Summary
• Getting the design ready for the prototype
  • Why “get the design ready to prototype?”
  • Adapting the design’s top level
  • Clock gating
  • Automatic gated-clock conversion
  • Selecting a subset of the design for prototyping
  • Handling RAMs
  • Handling instantiated SoC RAM in FPGA
  • Implementing more complex RAMs
  • Design implementation: synthesis
  • Prototyping power-saving features
  • Design implementation: place & route
  • Revision control during prototyping
  • Summary
• Partitioning and reconnecting
  • Do we always need to partition across FPGAs?
  • General partitioning overview
  • Automated partitioning
  • Improving prototype performance
  • Design synchronization across multiple FPGAs
  • More about multiplexing
  • Multiplexing schemes
  • Timing constraints for multiplexing schemes
  • Partitioning and reconnection: summary
• Design-for-Prototyping
  • What is Design-for-Prototyping?
  • Procedural guidelines
  • Integrate the prototype with the verification plan
  • Design guidelines
  • Guidelines for isolating target specificity
  • Clocking and architectural guidelines
  • Summary
• IP and high-speed interfaces.
  • IP and prototyping
  • IP in many forms
  • Soft IP
  • Peripheral IP
  • Use of external hard IP during prototyping
  • Replacing IP or omitted structures with FPGA IP
  • Summary
• Bring up and debug: the prototype in the lab
  • Bring-up and debug–two separate steps?
  • Starting point: a fault-free board
  • Running test designs
  • Ready to go on board?
  • Introducing the design onto the board
  • Debugging on-board issues
  • Note: use different techniques during debug
  • Other general tips for debug
  • Quick turn-around after fixing bugs
  • A bring-up and debug checklist
  • Summary
• Breaking out of the lab: the prototype in the field
  • The uses and benefits of a portable prototype
  • Planning for portability
• PROTOTYPING + VERIFICATION = THE BEST OF BOTH WORLDS
  • System prototypes
  • Required effort
  • Hybrid verification scenarios
  • Verification interfaces
  • Comparing verification interface technologies
  • Use models – more detail
  • Virtual platform as a testbench
  • System partitioning
  • Case study: USB OTG
• THE FUTURE OF PROTOTYPING
  • If prediction were easy. . .
  • Application specificity
  • Prototyping future: mobile wireless and consumer
  • Prototyping future: networking
  • Prototyping future: automotive
  • Summary: software-driven hardware development
  • Future semiconductor trends
  • The FPGA’s future as a prototyping platform
  • Summary
• CONCLUSIONS
  • The FPMM approach to FPGA-based prototyping
  • SoCs are larger than FPGAs
  • SoCs are faster than FPGAs
  • SoCs designs are FPGA-hostile
  • Design-for-Prototyping beats the three laws
  • So, what did we learn?