TABLE OF CONTENTS

• Preface
• Logic
  • Logic Gates
  • Binary
  • Adding with Logic
  • Flip-Flops
  • Shift Registers
  • Binary Counters
  • Summary
• FPGAs
  • How an FPGA Works
  • The Elbert 2
  • The Mojo
  • The Papilio
  • Software Setup
  • Project Files
  • Summary
• Drawing Logic
  • A Data Selector Example
  • A 4-Bit Counter Example
  • Summary
• Introducing Verilog
  • Modules
  • Wires, Registers, and Buses
  • Parallel Execution
  • Number Format
  • Data Selector in Verilog
  • A Counter in Verilog
  • Synchronous Logic
  • Summary
• Modular Verilog
  • A Seven-Segment Decoder
  • Button Debouncing
  • Multiplexed Seven-Segment Display and Counter
  • Summary
• Timer Example
  • State Machines
  • State Machine Design
  • Hardware
  • Modules
  • User Constraints File
  • The Timer Module
  • Testing
  • Summary
• PWM and Servomotors
  • Pulse-Width Modulation
  • A PWM Module
  • Servomotors
  • Hardware
  • A Servo Module
  • Summary
• Audio
  • Simple Tone Generation
  • Audio Output from the Mojo
  • A General-Purpose Tone/Frequency Generator
  • Playing an Audio File
  • Summary
• Video
  • VGA
  • VGA Timings
  • Drawing Rectangles
  • Making Things Move
  • A Memory-Mapped Display
  • Summary
• What Next
  • Simulation
  • Under the Hood
  • Cores and Soft Processors
  • More on the Papilio
  • More on the Mojo
  • Summary
• Resources
  • Components
  • Other FPGA Boards
  • Web Resources
• Elbert 2 Reference
  • Prototype Net Mapping
  • GPIO Pins
  • Clock
• Mojo Reference
  • NET Mapping (IO Shield)
  • Clock Pin
  • Complete UCF for IO Shield
• Papilio One Reference
  • LogicStart MegaWing NET Mapping
  • Clock Pin
  • GPIO Pins