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Xilinx FPGA FPGA Forum

“Traditional” Design Flows

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Defifinitions  

Let’s begin as usual by defining some terms we’ll encounter in this chapter.  

● Schematic is the common name for a circuit diagram.  

● Logic minimization or optimization means replacing one group of gates with  another that will perform the same task faster or use less real estate on the  silicon.  

● Gate-level design refers to a design represented as a collection of primitive  logic gates and functions and the connections between them.  

● Electronic design automation (EDA) is the name now applied to all of the CAE  and CAD tools used to design electronic components and systems.  

● Hardware description languages (HDLs) are computer languages used to  describe hardware, namely the electronic portions of ICs and printed circuit  boards.  

● Register transfer level (RTL) is a higher level of abstraction than HDL. In  RTL, the circuit is described as a collection of storage elements (registers),  Boolean equations, control logic such as if-then-else statements, and complex  sequences of events. The most popular languages used for capturing designs  in RTL are VHDL and Verilog (with SystemVerilog starting to gain a larger  following).

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