FPGA vs. ASIC Designs

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Defifinitions

Here are some terms we’ll be using in this chapter.

● Pipelining is analogous to an automobile assembly line, where the output of one logic block is the input of the next one. It will be explained in more detail in the following sections.

● Latency is the time in clock cycles that it takes for a specififi c block of data to work it way through a function, device, or system.

● Levels of logic refers to the number of gates between the inputs and outputs of a logic block.

● Combinational loops occur when the generation of a signal depends on itself feeding back through one or more logic gates.

● Delay chains are formed from a series of buffer or inverter gates and used for a variety of purposes, which we’ll discuss later in this chapter.

XC4VLX100-11FF1513I

Manufacturer:Xilinx
FPGA Virtex-4 LX Family 110592 Cells 90nm Technology 1.2V 1513-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS: No RoHS

XC4VLX100-11FFG1513C

Manufacturer:Xilinx
FPGA Virtex-4 LX Family 110592 Cells 90nm Technology 1.2V 1513-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS:

XC4VLX100-12FFG1148I

Manufacturer:Xilinx
FPGA Virtex-4 LX Family 110592 Cells 90nm Technology 1.2V 1148-Pin FCBGA
Product Categories:

Lifecycle:Unconfirmed -

RoHS:

XC4013E-3PG223C

Manufacturer:Xilinx
FPGA XC4000E Family 13K Gates 1368 Cells 0.35um Technology 5V 223-Pin CPGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Obsolete -

RoHS: No RoHS

XC3030A-7PG84C

Manufacturer:Xilinx
FPGA XC3000 Family 2K Gates 100 Cells 113MHz 5V 84-Pin CPGA
Product Categories:

Lifecycle:Obsolete -

RoHS: No RoHS

TABLE OF CONTENTS

FPGA vs. ASIC Designs