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In this chapter we will examine all aspects of the Zynq SoC design. We will take a closer look at certain aspects of the ARM processing cores and their operating modes, as well as laying down the foundations for some of the later chapters in this book. To be specific, the various interconnects available, interfacing signals, interrupts and the memory facilities on a Zynq device will all be introduced in this chapter, before being covered in greater detail as the book progresses.
One of the main objectives of this chapter is to detail the connections and shared resources that exist between the PS and the PL. These include the interconnect system, memories and a variety of different interfaces. Further, this chapter also describes the various operating modes of the Zynq SoC and the configurations of the PS and PL which can be used for different tasks and purposes.
As all Zynq-7000 AP devices feature the same dual-core ARM Cortex-A9 based PS, the information covered in this chapter can be applied across the entire Zynq range, unless otherwise stated. There are some small differences in certain models, mainly pertaining to the maximum operating frequency of the PS, and these will be explicitly mentioned in the relevant sections.
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Obsolete -
RoHS: No RoHS
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