Designing With Vivado High Level Synthesis

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Introduction

This tutorial presents an introduction to High Level Synthesis using the Vivado™ HLS environment. The creation of projects manually through the GUI, and automatically through scripting will be covered. The process of simulating, synthesising and analysing a Vivado HLS design will then be explored, with sufficient design optimisation and solution comparison along the way.

The tutorial is split into three exercises, and is organised as follows:

Exercise 3A — This exercise concerns the creation of projects using both the Vivado HLS GUI and use of Tcl scripting. It details the inclusion of relevant source and test files and generation of a project for use in the proceeding exercise.

Exercise 3B — This exercise involves design optimization of a matrix multiplication function through use of various directives. It presents the Vivado HLS design environment and method of synthesis and analysis of project solutions.

Exercise 3C — Finally, a more detailed look at how Vivado HLS synthesises interfaces is investigated.

XC1736DVC

Manufacturer:Xilinx
Xilinx SOP
Product Categories:

Lifecycle:Any -

RoHS: -

XC1736EPDG8C

Manufacturer:Xilinx
PROM Serial 35.44K-bit 5V 8-Pin PDIP
Product Categories: Memory - Configuration Proms for FPGA's

Lifecycle:Obsolete -

RoHS:

XC4013XL-09BG256C

Manufacturer:Xilinx
FPGA XC4000X Family 13K Gates 1368 Cells 0.35um Technology 3.3V 256-Pin BGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Obsolete -

RoHS: No RoHS

XC3S2000-4FG900C

Manufacturer:Xilinx
FPGA Spartan-3 Family 2M Gates 46080 Cells 630MHz 90nm Technology 1.2V 900-Pin FBGA
Product Categories: FPGAs

Lifecycle:Active Active

RoHS:

XC17512LPD8C

Manufacturer:Xilinx
PROM Serial 512K-bit 3.3V 8-Pin PDIP
Product Categories: Memory - Configuration Proms for FPGA's

Lifecycle:Obsolete -

RoHS: No RoHS

TABLE OF CONTENTS

Designing With Vivado High Level Synthesis

Introduction