Off-Chip and In-Chip Communications for FPGA Systems

While computing is the essence of integrated systems in general, and FPGAs in particular, it is evident that data need to be transported in order to be efficiently computed. For non-data-intensive applications, communica- tions may be neglected, and only computing-related issues are taken into account (computing performance, computing power, computing efficiency). However, for those application that work with large amounts of data (big data applications are the most representative ones), it is clear that communi- cations can be a key factor in the overall performance metrics. It is therefore required, for many applications, to be able to plan both computing and com- munication resources jointly. Moreover, it might be the case where perfor- mance is degraded because of communication overhead.

As was mentioned in Chapter 1, most systems require communicating with other external elements. The requirements of such off-chip communication are dependent on many factors: speed (both in data throughput and latency), reliability (sometimes packets of data may be lost, in other cases not), distance, environmental conditions, compatibility with networks, and so on. Therefore, there is no one solution that fits all. Although there are several classification possibilities, we have made a distinction between low-speed (Section 7.2.1) and high-speed ones (Section 7.2.2) due to their different implications in both internal and external FPGA designs. However, some distinctions between different technologies are also made, as well as between data-oriented and control- oriented communication interfaces (for the low-speed ones).

Since FPGAs integrate multiple computing resources, it is also necessary to establish some basics on how to efficiently implement communications between modules inside the chip. Although it would seem that internal communication resources are extremely versatile and there should be no problems in connecting as many elements as required, with direct connec- tions from the places where data are produced to the places where data are required, the architectural complexity of large designs impedes this straight- forward method. For instance, resource sharing forces to concentrate or dis- tribute data through communication structures from/to different elements, and therefore some arbitration is required. Fortunately, this is alleviated by the use of standardized interfaces that, for the purpose of module reuse, and with the help of automated tools to build complex SoPCs (see Chapter 6), let complex connection schemes to be built. This way, developing multiple buses, hierarchical buses, and bridged structures is somewhat easier. Examples of such arrangements have been addressed in Section 3.5 to describe the con- nectivity of embedded microprocessor cores. However, the scalability of such structures is a problem for large designs. Their performance worsens with an increase in the number of connected modules for two reasons: data access sat- uration, produced by an increasing number of modules willing to access the same communication resource, and maximum speed (i.e., data throughput degradation), because of the increased distances to be covered between dis- tant modules. Although heavily pipelined structures might partially resolve this last issue, the growing complexity of large SoPC designs might lead to the need of settingup networks-on-chip (NoCs) as a shared mechanism to link a larger number of interconnected modules, providing a structure that enables simultaneous connections at the same time, with no such speed ( frequency) degradation when the system scales up in size. In-chip communications are addressed in Section 7.3, covering point-to-point communications, bus-based connections, and NoCs in its three different subsections.

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