Tools and Methodologies for FPGA-Based Design

Tools and methodologies for FPGA-based design have been continuously improving over the years in order for them to accommodate the new and extended functionality requirements imposed by increasingly demanding applications. Today’s designs would take unacceptable extremely long times to be completed if tools coming from more than 20 years ago were used. The first important incremental step in accelerating design processes was the replacement of schematic-based design specifications by HDL descriptions (Riesgo et al. 1999).* On one hand, this allows complex circuits (described at different levels of abstraction) to be more efficiently simulated, and on the other hand, designs to be quite efficiently translated (by means of synthesis, mapping, placement, and routing tools) from HDLs into netlists, as a step previous to its translation into the bitstream with which the FPGA is config- ured (as described in Section 6.2.3.4). 

Conventional synthesis tools were quite rapidly adopted by designers due to the productivity jump they enabled. At that point, it soon became apparent that FPGAs were very well suited to rapid prototyping and emu- lation flows because very little HDL code rework (or even none at all) was required in order to migrate designs initially implemented in FPGAs to other technologies. Either for prototyping or for final deployment, FPGAs rapidly increased their market share. As a consequence, and thanks to the improvement in manufacturing technologies, their complexity was continu- ously increased to cope with the ever-growing demand for more and more complex and integrated systems. This, in turn, contributed to higher market penetration, which pushed for additional complexity and expanded func- tionality, and so on. 

The fast adoption of conventional synthesis tools as part of the natural design process for all types of digital hardware devices was not as fast, however, in the case of HLS tools (Cong et al. 2011). The difference between both types of tools resides in clock cycle explicitness. A conventional synthe- sizable HDL file mostly consists of descriptions where the transfers between memory elements can be directly and explicitly inferred from the code, clock cycle by clock cycle. In contrast, HLS tools start from descriptions that do not explicitly specify clock activity, but work at algorithmic level instead. The contribution or refinement HLS tools provide is their ability to allocate logic resources or operators and assign functions to such operators within the required time slots so that the algorithm may be mapped to a circuit with efficient resource sharing. Additionally, logic functions can be extended into optimized pipelined structures (so that the translation of such slots into clock cycles makes timing explicit), and clock speed can be optimized by ade- quately balancing critical paths within the pipelined structures. Regarding memories, different accessing schemes enable variable bandwidth adjust- ment so that it may adequately fit the functions being carried out by the logic reading/writing data from/to such memories. Finally, HLS tools also support two I/O types: memory mapped and stream based. These issues are analyzed in detail in Section 6.4. 

Traditional or HLS tools alone cannot support the design of many of today’s complex FPGA embedded systems. They need to be combined with platform-based tools that, in essence, automate different processes within a SoPC design flow (Sangiovanni-Vincentelli and Martin 2001). These tools combine standard components from integrated IP libraries with custom- made blocks designed using either conventional or HLS flows. Most current embedded systems are not fully customized designs, but rely on the combi- nation of some standardized functions and interfaces with custom-made IP blocks. Therefore, module reuse and automated tools are mandatory in order to speed up the design process. Complex systems may be built with relatively little designer intervention if the design is based on library modules con- nected with standardized on-chip interfaces (described in Section 3.5). These tools provide, among many other features, module customization, automatic connection, automated memory map generation, as well as easy access to software code programmers by means of hardware abstraction layers for easy hardware/software interfacing. Users not familiar with this design method- ology may be astonished to see how it allows highly complex designs to be readily obtained. For instance, a dual-core processor system with complex DMA schemes providing efficient access to a gigabit Ethernet media access control layer, plus some other I/O interfaces (such as SPI, I 2 C, USARTS, or GPIO), can be built in only a few hours. 

Other tools are currently available whose design languages allow explicit parallelism to be described, aimed at achieving the maximum possible algo- rithm acceleration in HPC applications. They are based on OpenCL, which allows multithread parallelism to be mapped to heterogeneous computing platforms, such as FPGAs (Altera 2013; Xilinx 2014). In the last years, the main FPGA vendors are continuously releasing new specialized tools to ease the translation from OpenCL code into FPGA designs. These tools also provide ways for designs running in a host, usually a computer, to be accelerated by attaching one or more FPGA boards to it, often by means of PCIe connections (described in Section 2.4.4.1). 

Increasingly, complex tools and design flows must necessarily be comple- mented with suitable validation and debugging methods. Verification can (and should) be done at early design stages, prior to circuit configuration, by means of simulation techniques. These techniques may be performed at functional level, to validate logic functionality, or after placement and rout- ing, where accurate timing data are available to be annotated into the simula- tion. Very interestingly, as highlighted in Section 6.6.1.2, it is also possible to use integrated logic analyzers (embedded into the FPGA) for debugging pur- poses. These elements allow for combined hardware/software evaluation, which is very useful, especially for SoPC designs. Although some structured design validation techniques do exist, such as those derived from formal verification methods, they are not addressed in this book for two reasons: They are not specific to FPGA design and, to the best of authors’ knowledge, there are no such commercial tools available for industrial use. 

In the following sections, the different tools and design flows currently available are described in order of increasing complexity, which also cor- responds with their evolution over time. Therefore, the conventional flow to transform netlists into bitstreams, based on the combination of register- transfer level (RTL) synthesis with back-end tools, is described in Section 6.2. Section 6.3 deals with the design flows and associated frameworks for SoPC systems, available for medium- and high-end FPGAs. HLS tools are dis- cussed in Section 6.4. Contrary to what one might think, they appeared after SoPC platform-based designs, in part due to the slow adoption of these tools also in other areas, such as ASICs. In Section 6.5, tools for multithread acceleration in HPC applications are described. Finally, debugging tools and some second-order (or optional) tools available in many FPGA design frame- works are addressed in Section 6.6.