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There are several factors that inflfl uence the power consumption of a given system and can be divided into two broad categories—physical and functional. Board design, packaging, and device selections are examples of physical factors, whereas functionality is largely related to the RTL design itself. In this chapter, we will explore the tools available for power estimation and optimization. Power estimation can be done at various levels of granularity, and the accuracy of the estimation is dependent on the amount of information you can provide. The more information you can provide, the more accurate the estimates will be compared to the power consumption on the fifi nal hardware. Xilinx provides three tools to help analyze and optimize for power (see Fig. 15.1 ). These are:
1. Xilinx Power Estimator ( XPE ): This is used for predesign phase estimation. This is an Excel-based tool and relies heavily on user-entered information in both physical and functional categories. While XPE is very helpful in doing power budgeting in the early phase of a project, it can also be used to do a what-if analysis for an implemented design.
2. Vivado Report Power : This is used for post-design phase power analysis. This is a more accurate tool as it operates on a synthesized, placed, or routed netlist. While majority of the functional information is obtained from the netlist, you still need to enter the physical factors and switching activity information to get an accurate power estimation.
3. Vivado Power Optimization : This implements ASIC style clock- gating technique based on sequential analysis of the designs. It reduces the activity on portions of the design that do not impact the design output.FPGA power can vary from few hundreds of mW to tens of Watts. It depends on a variety of factors – design function, clock frequency, switching activity, and board and environmental setup. Power on an FPGA can be broadly divided into four categories:
• Device Static : This is the power which is consumed even if there is no design configured into FPGA. This is typically measured by programming a blank bitstream into the device and is a function of process, voltage, and temperature.
• Core Dynamic : This is the dynamic power consumed when the FPGA is in use and does not include I/O and Transceiver power.
• I/O and Transceiver: Power in I/O and Transceivers is categorized separately as they have a high impact on overall power. The tools provide a capability to explore various confi gurations to make the best possible decision from power standpoint.
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