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Introduction to Timing Concepts
Timing closure involves modifying constraints, design, or tool flfl ow/settings to meet timing requirements. In Vivado tool, the timing constraints are entered in XDC format. XDC constraints are based on the standard Synopsys Design Constraints (SDC) format. For brevity all the constraints that Vivado supports are not explained in this chapter but only few are given to help understand topics discussed later in this chapter. For details on XDC constraints and syntax, please refer to UG903 published by Xilinx.
Creating and Defifi ning a Clock
create_clock Tcl command allows user to defifi ne clock on a certain port and also allows users to specify properties like period, waveform, root, etc. Unless a clock is defifi ned using the create_clock command, static timing analysis is not performed on the clock. Also, create_clock command defifi nes primary clocks, and all derived clocks are automatically inferred. Usually the derived clocks come from the clock modifying blocks like MMCM and PLL.
Defifi ning Clock Relationships
Like all other SDC-based tools, Vivado also does timing analysis on all the cross- clock paths. However, designers in certain occasions would want to ignore certain paths, because those paths are either static paths (no signal transition happens) or the paths are asynchronous and hence should not be timed. In such cases set_clock_groups or set_false_path commands are used to preclude certain portions of the designs from timing analysis. This is an essential step as ISE (the previous Xilinx tool) which used UCF constraints, assumed the opposite, i.e., unless clock relationship was specififi ed, timing analysis was not done on cross-clock paths.
Timing Analysis
Given these basic defifi nitions of creating clock constraints and specifying clock relationships, Vivado’s timing analysis engine does several checks under the static timing analysis engine. The timing analysis engine analyzes and reports slack at the timing path endpoints. The slack is the difference between the data required time and the data arrival time at the path endpoint. A data is safely transferred between two registers if both the setup and hold relationships are successfully verififi ed on that path. In other words, if both setup and hold slacks are positive, the path is considered good from a timing point of view. The following are the checks performed by Vivado’s timing analysis engine:
• Setup check
• Hold check
• Pulse-width check
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