Cross Clock Domain Handling - Sub-stable and Synchronizer
The design of digital circuits usually requires special handling when it comes to cross-clock domain (CDC) circuits, such as synchronizers, asynchronous FIFOs, and so on. So why CDC needs special treatment, and what problems will result if it is not done.
Date: Jul 12, 2021
From this article you will get more information about reset circuit. The reset circuit is to use it to restore the circuit to the initial state.
Date: Aug 13, 2020
Dynamic aging test of FPGA integrated circuits
For the dynamic aging test of FPGA circuits, the function test code is the configuration program stored in the external memory.
Date: Jul 07, 2020
Monostable circuit based on CPLD device design
In CPLD devices, the input narrow pulse can be widened; of course, the input wide pulse can also be narrowed.
Date: Jul 07, 2020
Button debounce and single pulse generator circuit in FPGA development
In order to make the key debounce circuit module simple and transplantable, the key debounce function is implemented in the form of a counter.
Date: Jul 07, 2020
Realization of VGA color picture display based on FPGA
The common color display with VGA interface is generally composed of cRT (cathode ray tube), and the color is composed of three primary colors of R, G, and B (red: Red, green: Green, and blue: Blue).
Date: Jul 07, 2020
Enhance FPGA applications with programmable oscillators
The inherently programmable silicon MEMS clock oscillator architecture can help system designers using FPGAs to solve many problems.
Date: Jul 07, 2020
Design of BPSK signal carrier frequency estimation unit based on FPGA
BPSK, or binary phase shift keying, is a modulation method often used in direct-spread signals. The phase change of the carrier is used to transmit digital information, and the amplitude and frequency of the signal are kept constant.
Date: Jul 07, 2020
Talk about xilinx FPGA configuration circuit
Digital phosphor oscilloscope (DPO) is an oscilloscope platform launched by Tektronix. It has various traditional advantages of digital storage oscilloscopes, such as data storage and advanced triggering functions.
Date: Jul 07, 2020
Independent key detection for FPGA learning
From this article, you will get more information about Independent key detection for PGA learning, so you just need to read it carefully.
Date: Jul 07, 2020
Xilinx QFP
FPGA Spartan-II Family 100K Gates 2700 Cells 263MHz 0.18um Technology 2.5V 456-Pin FBGA
FPGA XC3000 Family 1.5K Gates 64 Cells 100MHz 5V 68-Pin PLCC
Xilinx PLCC
Xilinx PLCC
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