How to implement NVMe SSD interface on Xilinx ZCU102 evaluation kit

This article shows a solution to implement the NVMe solid-state drive (SSD) interface on Xilinx’s ZCU102 evaluation kit by using Design Gateway’s NVMeG3-IP core. This solution can achieve amazingly fast performance: write speeds of 2,319 MB/s, read The fetch speed is 3,347 MB/s.

Date: Dec 02, 2020

Use FFT IP Core to implement FFT algorithm

This design uses Altera's FFT IP Core to realize the FFT function, which can realize the FFT conversion of two 256-point real data at the same time, and perform the modulo square operation on the conversion result. The design has the ability to continuously process the data.

Date: Aug 20, 2020

Implementation of custom buffer management based on FPGA and IP Core

From this article you will get more information about implementation of custom buffer management based on FPGA and IP Core, so you just need to read it carefully.

Date: Aug 06, 2020

Realization of IP protection based on EDA or FPGA

From this article, you will get more information about realization of IP protection based on EDA or FPGA , so you just need to read it carefully.

Date: Aug 03, 2020

Responding to new challenges in video transmission with energy-efficient IP cores

In the codec link, VeriSilicon cooperated with Google to launch the new Hantro G2 video decoder IP, which is the only one in the industry that can support the latest HEVC and VP9 video formats at the same time, and supports 4K resolution and 60 frames per second with a single cor...

Date: Jul 23, 2020

Integrate data converter IP into system chip to simplify design technology

In order to maximize the IP performance of the data converter, the system chip designer must deal with the challenge of integrating the data converter with the system chip and avoid defects that jeopardize the performance of the entire system.

Date: Jul 08, 2020

ARM responds to the scuffle of giants such as Intel with a unique survival mode

With the disclosure of the new 22nm SoC process and the new Atom architecture, Intel has finally begun to show its power.

Date: Jul 08, 2020

Synopsys high-performance vision processor IP addresses machine vision megatrends

A general-purpose processor (GPP) can be used for visual processing, but such a processor lacks the resources of complex mathematical operations and will run very slowly.

Date: Jul 08, 2020

Implementation of ASI sending card based on Altera ASI IP core

ASI can have different data reception rates, but the transmission rate is constant at 270 Mbit/s.

Date: Jul 07, 2020

Pulse Compression of LFM Signal Based on FPGA IP Core

Taking this as the starting point, this paper studies and simulates the pulse compression of the chirp signal, and proposes a method for designing pulse compression using the IP core.

Date: Jul 07, 2020