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Home > FPGA Technology > FPGA > Zynq-7000 Series Quad-SPI Flash Controllers Explained - FPGA Technology

Zynq-7000 Series Quad-SPI Flash Controllers Explained

Date: Jul 05, 2021

Click Count: 37

Introduction

The Quad-SPI flash controller is part of an input/output peripheral (IOP) located within the PS that is used to access multi-bit serial flash devices for high throughput and low pin count applications.


The controller operates in one of three modes.

  • I/O mode


  • Linear addressing mode


  • Traditional SPI mode


In I/O mode, software interacts closely with the flash device protocol, using the four TXD registers to write flash commands and data to the controller, and software reads the RXD register containing the data received from the flash device.


Linear addressing mode uses a subset of device operations to eliminate the software overhead required for I/O mode reads of the Flash memory. Linear mode uses hardware to issue commands to the Flash memory and control the flow of data from the Flash bus to the AXI interface, and the controller responds to memory requests on the AXI interface as if the Flash were a ROM memory.

In legacy mode, the QSPI controller acts as a normal SPI controller.


The controller can be connected to one or two flash devices, and the two devices can be connected in parallel for 8-bit performance or in a stacked 4-bit arrangement to minimize pin count.


What are the features

  • 32-bit AXI interface for linear addressing mode transfers


  • 32-bit APB interface for I/O mode transfers


  • Programmable bus protocol for Micron and Spansion flash memory


  • Legacy SPI and scalable performance: 1x, 2x, 4x, 8x I/O widths


  • Flexible I/O

  1. Single SS 4-bit I/O flash interface mode

  2. Dual SS 8-bit parallel I/O flash interface mode

  3. Dual SS 4-bit stacked I/O flash interface mode

  4. Single SS, legacy SPI interface


  • 16 MB addressing per device (32 MB for two devices)


  • For I/O and linear modes, device densities up to 128 Mb, I/O modes support densities greater than 128 Mb.


  • I/O mode (flash command and data)

  1. Software issues commands and manages flash operations

  2. FIFO controlled interrupts

  3. 63-word RxFIFO, 63-word TxFIFO


  • Linear addressing mode (read accesses can be performed)

  1. Memory reads and writes are interpreted by the controller

  2. AXI ports can buffer up to four read requests

  3. AXI incremental and wrap-around address functions


System view

The Quad-SPI flash controller is part of the IOP and connects to the external SPI flash via MIO, as shown in Figure. The controller supports one or two memories.

1.png


Address Mapping and Device Matching for Linear Address Mode


When using a single device, the address mapping for direct memory reads starts at FC00_0000 and goes up to FCFF_FFFF (16 MB).


Address mapping for dual-device systems depends on the memory device and I/O configuration. In dual-device systems, Quad-SPI devices need to come from the same vendor, so they have the same protocol.


The 8-bit parallel I/O configuration also requires that the devices have the same capacity, and the address mapping for the parallel I/O configuration starts at FC00_0000 and continues to the address of the combined memory capacity up to FDFF_FFFF (32 MB).


For 4-bit stacked I/O configurations, devices can have different capacities, but must have the same protocol.


If two devices of different sizes are used, Xilinx recommends using a 128 Mb device at the lower address, in which mode


  • QSPI 0 devices start at FC00_0000 and reach the maximum value of FCFF_FFFF (16 MB).

  • QSPI 1 devices start at FD00_0000 and reach a maximum of FDFF_FFFF (16 MB).


If the size of the first device is less than 16 MB, then there is a memory space hole between the two devices.


Block Diagram


The block diagram is shown in the figure.

2.png


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