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Home > FPGA Technology > FPGA > Zynq-7000 Series On-Chip Memory (OCM) Introduction - FPGA Technology

Zynq-7000 Series On-Chip Memory (OCM) Introduction

Date: Jul 20, 2021

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Introduction to On-Chip Memory (OCM)

The On-Chip Memory (OCM) module contains 256 KB RAM and 128 KB ROM (BootROM), which supports two 64-bit AXI slave interface ports, one dedicated to CPU/ACP access via the APU Supervisor Control Unit (SCU) and the other shared by the Processing System (PS) and all other bus masters within the Programmable Logic (PL). The BootROM memory is dedicated to the boot process and is not visible to the user.


The OCM supports high AXI read and write throughput for RAM accesses by implementing the RAM as a double-wide memory (128-bit), and to take advantage of the high RAM access throughput, user applications must even use AXI burst sizes and 128-bit aligned addresses.


TrustZone functionality is supported at 4 KB memory granularity, where the entire 256 KB RAM can be divided into 64 4 KB blocks with independently assigned security attributes.


As shown, there are 10 AXI channels associated with the OCM, five for the CPU/ACP (SCU) port and five for other PS/PL master devices (OCM switch ports).


Arbitration between the SCU and OCM switch port read/write channels is performed within the OCM module, parity generation and checking is performed for RAM accesses only, and the other main interfaces are the interrupt signal (IRQ ID #35) and the register access APB port.


On-Chip Memory (OCM) Block Diagram

On-Chip Memory.png

On-Chip Memory (OCM) Features

The main features of the OCM include


  • On-chip 256 KB RAM

  • On-chip 128 KB BootROM (not visible to the user)

  • Two AXI 3.0, 64-bit slave interfaces

  • Low latency path for CPU/ACP reads to OCM (CPU frequency of 667 MHz - minimum 23 cycles)

  • Cyclic pre-arbitration between read and write AXI channels on OCM interconnect ports (non-CPU ports)

  • Fixed priority arbitration between CPU/ACP (via SCU) and OCM interconnect AXI ports

  • Support for synchronous read and write commands with full AXI 64-bit bandwidth on OCM interconnect ports (with optimal alignment constraints)

  • Supports random access to RAM from AXI master devices TrustZone supports on-chip RAM with 4 KB page granularity

  • Flexible address mapping capability

  • RAM byte parity generation, checking and interrupt support

  • Support for the following non-AXI functions on the CPU (SCU) port.

  1. Zero line padding

  2. Prefetch prompting

  3. Early BRESP

  4. Presumptive line prefetch


On-Chip Memory (OCM) System View

The system view of OCM is shown in the figure.

On-Chip Memory-2.png

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