This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Technology > FPGA > Xilinx FPGA MIPI interface briefly explained - FPGA Technology

Xilinx FPGA MIPI interface briefly explained

Date: Jan 18, 2022

Click Count: 762

Xilinx's MIPI solution. Here the common 7 series as the object of discussion, the X family of high-end KU + / MPSOC + has been able to directly support the MIPI interface IO.

Since the MIPI signal is special, the low power consumption should be fully considered at the beginning of the design, so the MIPI native signal level supports HS and LP modes, working at different level standards:


From the diagram, it is clear that MIPI electrical signals exist in 2 level modes at the same time, which is obviously not supported by FPGA if it is connected to FPGA pins.

At the same time, the HS mode level standard is also not supported by FPGA. Therefore, the Xilinx family gives 2 kinds of programs to achieve the conversion of MIPI signal level, this has a detailed description in the document XAPP894, only the MIPI DPHY Rx part is given below

1 resistor network

2resistor network.jpg

In the case of high MIPI line rate, it is not recommended to use this method.

2External chip MC20901

When used to receive the camera, only MC20901 is needed


About the debugging of MIPI

The premise of MIPI debugging is that you have completed the correct configuration of the sensor, it is recommended to get a set of verified configuration from the Internet or FAE to drive the sensor, so that the next debugging focus can be placed on the MIPI part. (To add, one of the concepts I remember most from high school biology is: to do experiments to control variables, to meet the single variable to repeat the comparison test to explain the question. However, in the work, many times out of the question to locate are wild guesses)

Since the use of the four Xilinx MIPI RX Subsystem IP solution, so the user can configure the part is actually not much. But this Subsystem internal is actually 2 IP composition, one is the MIPI-DPHY, the other is the MIPI-CSI2 interface, and then the two IPs are interconnected using the PPI interface.

The MIPI DPHY receives the bitstream data and then recovers the packet according to the frame format. the protocol has ECC checksum for the packet, which has certain ability to identify and correct errors. However, if the signal quality is not good and there are more errors, there will be unrecoverable errors, which are displayed on the image as flying lines or even splash screen caused by incorrect timing.

After the synthesis is completed, open the synthesized schematic, enter the MIPI DPHY section, mark_debug the signal with the physical layer suffix err, and then save it to the xdc file for later debugging


From the figure you can see the xilinx MIPI IP PPI interface errorths signal pulled up, indicating the existence of line loss, the situation, if the physical layer error signals constantly, and then after checking the FPGA project itself no problem, then you can consider whether there is a problem from the hardware side.

<< Previous: Basic knowledge of FPGA architecture and applications

Need Help?


If you have any questions about the product and related issues, Please contact us.