Xilinx-7 Series FPGA high-speed transceiver use learning

The main difference between the four types of transceivers is the different line rates supported. Figure 1 illustrates the device types and the types of transceivers supported as well as the maximum number of transceivers in the 7 series.

Xilinx's 7 series FPGA with increased integration, its high-speed serial transceivers no longer exclusive a separate reference clock, but to Quad to serial high-speed transceivers to group, four serial high-speed transceivers and a COMMOM (QPLL) to form a Quad, each serial high-speed transceivers called a Channel, to XC7K325T For example, the GTX is inside the FPGA as shown in the figure.

For each serial high-speed transceiver, which contains a transmit part and a receive part, the internal structure is as follows.

The transmitter and receiver are functionally independent and both consist of two sublayers, PMA (Physical Media Attachment) and PCS (PhysicalCoding Sublayer). The PMA sublayer contains circuits such as high-speed serial/parallel conversion (Serdes), pre/post-emphasis, receive equalization, clock generator and clock recovery, etc. The PCS sublayer contains circuits such as 8B/10B codec, buffer, channel binding and clock correction.

GTX transmitter processing flow: first user logic data after 8B/10B coding, into a transmit buffer, the buffer is mainly the PMA sub-layer and PCS sub-layer two clock domain clock isolation, to solve the two clock rate matching and phase differences, and finally through the high-speed Serdes for parallel-serial conversion, if necessary, can be pre-emphasis, post-emphasis. It is worth mentioning that if the TXP and TXN differential pins are inadvertently cross-connected during PCB design, this design error can be compensated by polarity control. The receiver side and the transmitter side processes are opposite and have more similarities, so we won't go over them here. What needs to be noted is the elastic buffer at the RX receiver side, which has clock correction and channel binding functions.

The above is an overview of the GTX performance and structure functions, the following detailed analysis of the GTX clock structure.

In the case of the Series 7 GTX, each Quad has two external differential reference clock sources, and the clock structure of one of the Quads is shown in the following figure.

The red box section is the two differential reference clock inputs, and each external reference clock input must pass through the IBUFDS_GTE2 source language before it can be used. The green box is the reference clock input from other Quad. The 7 series FPGAs support using the reference clock of the adjacent (north-south) Quad as the reference clock of the current Quad. The multiple reference clock sources are divided into two ways into QPLL and CPLL after a selector, as shown in Figure 5 and Figure 6, where the blue box is QPLL and the yellow box is CPLL, for a GTX Channel, the reference clock can be independently selected, either QPLL or CPLL, the difference between QPLL and CPLL is that the two support different line rates, QPLL supports a higher line rate than CPLL, Figure 7 is the detailed structure of the external reference clock model, the red arrow indicates the QPLL path, the yellow arrow indicates the CPLL path.

Because there are two external reference clocks for each Quad, two different reference clocks can be selected for each Quad. The receiver and transmitter of each CHANNEL can select the reference clock independently, as shown in the following figure.

If the user needs to use another Quad's reference clock source as the current Quad's reference clock, the following three conditions can be used if they are met.

1. only the reference clock of the Quad above the current Quad can be used.

2. only the reference clock of the Quad below the current Quad can be used.

3. a Quad's reference clock source cannot drive more than three Quad's transceivers (only the current Quad and the two adjacent Quads above and below).

Meet the above conditions, you can configure the reference clocks of other Quads as the reference clock of the current Quad, as shown in Figure IX. Note that the red boxes in the figure indicate the adjacent Quads.

The difference between QPLL and CPLL lies in the different line rates supported by both, for CPLL, the supported line rate bits between 1.6GHz and 3.3GHZ, while for QPLL, the line rate supported by GTX is divided into two classes, Lower Baud supports 5.93GHz~8.0GHz, Upper Baud supports 9.8GHz~12.5GHz, and for GTH, the line rate supported by GTX is divided into two classes, Lower Baud supports 5.93GHz~8.0GHz, Upper Baud supports 9.8GHz~12.5GHz. 12.5GHz, for GTH is not divided into grades, the supported line rate is 8.0GHz ~ 13.1GHz.