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EDK simulation of Xilinx 7 series (KC705/VC709) FPGA

Date: Nov 21, 2020

Click Count: 41

Overview

Some time ago, I communicated with some customers about some learning methods of PCIe, especially about the EDK simulation of Xilinx 7 series (KC705/VC709) FPGA. Therefore, FPGAKey feels it is necessary to write an article to share with you. Any questions are welcome. Get in touch with us.

After Xilinx is upgraded to the 7 series, the original PCIe IP nuclear trn interfaces are all converted to axis interfaces, which embarrassed the friends who used xapp1052 before, and were not used to it or not easy to use, what should I do? My thoughts on this are: if you have about two years of Verilog code experience, I suggest you use the axis interface directly. If you find it inconvenient to use, you can wrap a layer of an interface that you feel is easy to use. PCIe_to_RapidIO, PCIe_to_FC, PCIe_to_Enet and other interface conversions are all right.

If you are new to PCIe and want to have a clearer understanding of how the PCIe IP core of the axis interface works, then this system-level blog will be very useful to you. At the same time, the blogger will also give a band with Block_design. For a simple EP with DMA function, you can operate the DMA on the EP side by writing a simple control logic yourself, which is a relatively easy technology migration for inexperienced engineers.

Xilinx 7 series (KC705/VC709) FPGA products:

Virtex-7 FPGAs, Artix-7 FPGAs, XA Artix-7 FPGAs, Kintex-7 FPGAs

Preliminary preparation

1. You must have a PCIe foundation, especially the protocol part. If you don't have this foundation, please find the relevant information yourself. This is the prerequisite for learning and understanding Xilinx 7 series (KC705/VC709) FPGA.

2. Vivado2015.4 suite

3. Modelsim64_10.5

Specific steps

In the first part, we want to generate a PCIe RP end, the specific operations are as follows:

Open vivado, quickly generate an example design, select base MicroBlaze, and generate it according to the default settings. Manually add axi_memory_maped_to_pcie, axi_abram_ctrl; According to the design requirements of the EP side, set the RP side PCIe core. In this design, the link uses 4x, 5G, reference clock 100M, Bar0 space 64K, address width 32 bits, data width 128 bits, C_AXIBAR2PCIEBAR_0=0xFFFF0000 ( Bar0 address on EP side), C_PCIEBAR2AXIBAR_0=0x06000000 (BRAM base address on RP side) set gpio to output, 32bit. Set Bram to 128 bits. Then automatically connect, and finally Generate Block Design, generate the RP end system framework as follows:

Generate RP end system framework.jpg

Block Design.jpg

The external ports of Create HDL Wrapper are as follows:

module pcie_rp_wrapper

(

output [31:0] gpio_tri_o,

input [3:0]pcie_7x_mgt_rxn,

input [3:0]pcie_7x_mgt_rxp,

output [3:0]pcie_7x_mgt_txn,

output [3:0]pcie_7x_mgt_txp,

input reset,

input rs232_uart_rxd,

output rs232_uart_txd,

input sys_diff_clock_clk_n,

input sys_diff_clock_clk_p

)

3. FILE-Export-Export hardware, generate hdf files, File-Launch SDK;

4. Enter SDK, file-new-board support packet, and generate BSP on this hardware platform.

file-new-board support packet.jpg

5. Build a C-project based on BSP. Here we will not create a new project, but use pcie's example as an example. Click on the red box import example in the above figure and select the RC enumeration example.

C-project.jpg

After building the project, you can see the corresponding elf file in the debug directory.

6. Modify the rc_enmuerate_example.c file.

  • Need to modify the following places:

  • Remove all printing and use gpio output instead of printf

  • Refer to xgpio_example.c, add gpio initialization, output direction and other settings in rc_enmuerate_example.c; change PCIE_CFG_BAR_0_ADDR to 0xFFFF0000 to ensure that the bar0 base address written into the EP configuration space during enumeration is PCIE_CFG_BAR_0_ADDR

  • Modify the link_up part of the PcieInitRootComplex function, use the do-while statement to ensure that RP and EP can link_up;

  • Copy all the .h files from the SDK installation directory E:\Xilinx\SDK\2015.4\data\embeddedsw\XilinxProcessorIPLib\drivers\axidma_v9_0\src to bsp\microblaze_0\include where the SDK project is located, and copy all the .c files to In the src directory, refer to the xaxidma_example_simple_intr.c file to configure DMA. Pay special attention to the XAxiDma_ConfigTable in xaxidma_g.c according to the design of our ep end. There are many things that need to be modified in DMA, mainly the Rx buffer and Txbuffer addresses when DMA sends and receives data because MicroBlaze is on the RP side and DMA is on the EP side. In this example, when we first fill in the Txbuffer through MicroBlaze, the Txbuffer address uses the EP side BRAM address seen by the RP side. When DMA sends data, the Txbuffer address uses the BRAM address seen by the EP side. If you cannot understand it accurately, please purchase the accessory project. Modify some definitions, there are many for loops in the code, too many times affect the simulation.

7. Build the project, and generate the elf file in the project_2.sdk\helloword_bsp_xaxipcie_rc_enumerate_example_1\Debug directory.

8. Open vivado, right-click the board design and associate the elf file with our RP-side board design, and the RP-side software and hardware design are complete.

In the second part, we have to design our PCIe EP end, the specific operations are as follows:

On the basis of the first part, use ip integrator-create block design, named Pcie_ep_dma. Add ip core: axi_memory_maped_to_pcie, axi_abram_ctrl, axi_direct_memory_access, axi_interconnect. Set the EP side pcie core, the link in this design uses 4x, 5G, reference clock 100M, Bar0 space 64K, address width 32 bits, data width 128 bits, C_AXIBAR2PCIEBAR_0=0xEEEE0000 (bar0 address on RP side), C_PCIEBAR2AXIBAR_0=0x08000000 (EP side BRAM base address). Set the bram data bit width to 128bit. The remaining connections are as follows.

PCIe EP frame.jpg

Pcie_ep_dma.jpg

The external ports of Create HDL Wrapper are as follows:

entity Pcie_ep_dma_wrapper is

port (

REFCLK: in STD_LOGIC;

pcie_7x_mgt_rxn: in STD_LOGIC_VECTOR (3 downto 0 );

pcie_7x_mgt_rxp: in STD_LOGIC_VECTOR (3 downto 0 );

pcie_7x_mgt_txn: out STD_LOGIC_VECTOR (3 downto 0 );

pcie_7x_mgt_txp: out STD_LOGIC_VECTOR (3 downto 0 );

reset: in STD_LOGIC

);

end Pcie_ep_dma_wrapper;

After completion, generate output product for the EP and RP block designs. Choose global integration.

The third part is to connect the EP end and RP end to simulate. The testbench is too simple. I won't talk about it here. Connect the PCIe of EP and RP, connect the clock, and reset to simulate. The simulation results are as follows:

From EP->RP:

EP-RP.jpg

From RP to EP:

RP to EP.jpg

The waveform on AXI_Dma:

Waveform on AXI_Dma.jpg

Because the sent length is set to 256 bytes, the time for one DMA is very short.

Concluding remarks

Xilinx 7 series (KC705/VC709) FPGA EDK simulation problems are introduced here. If you have any questions, please contact FPGAKey or discuss them in the forum.


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