Date: Nov 02, 2022
Click Count: 141
SDRAM has a synchronization interface that waits for a clock signal before responding to a control input to synchronise it with the computer's system bus.
The clock drives a finite state machine that performs Pipeline operations on incoming instructions.
This allows the SDRAM to have a more complex mode of operation than asynchronous DRAMs that do not have a synchronous interface.
Pipelining means that the chip can accept a new instruction before it finishes processing the previous one.
In a write pipeline, the write command can be executed immediately after another instruction is executed without waiting for data to be written to the memory queue.
In a read pipeline, the required data arrives after a fixed number of clock frequencies after the read instruction is issued. This waiting process allows other additional instructions to be issued.
This delay is called Latency and is an important parameter when purchasing memory for a computer.
SDRAM has been widely used in computers from the beginning of SDRAM to the subsequent generation of DDR (or DDR1), then DDR2 and DDR3 entered the mass market, and DDR4 entered the consumer market starting in 2015.
Dynamic memory drivers are more complex than static memory drivers... We need rows, columns and memory bodies, and refresh cycles to handle them. But SDRAM is compelling due to its high speed and low cost per unit.
So we needed a way to access SDRAM with easy access to static memory. This is the reason for creating memory controllers. They act as a conversion layer: they provide the user with an easy-to-use memory interface and then do the tedious work of driving the real SDRAM signals.
If we look at the SDRAM pins, then there are some newcomers.
The address and data buses are still present, but the address bus is only 11 bits (used to provide the row to be opened and then the column address).
The BA pin specifies the memory area (since, in our example, there are only 2 memory areas, we only need one pin).
The WE, CAS and RAS are used together as command pins, so we can send 8 different commands to the SDRAM (commands like "open row", "read", "write ", and "close row").
Some other pins are used (but not shown in the picture), such as clock, chip select, and byte enable...
Note that in dynamic memory, the "open line" is called active, and the "close line" is called pre-charge.
SDRAM is a dynamic memory: since each memory bit value (0 or 1) is stored in a tiny capacitor, the charge decays over time, so its contents need to be refreshed periodically. But the decay rate is low enough that manufacturers can guarantee that no data will be lost as long as it is read and re-written ("refreshed") periodically.
There are two refresh mechanisms.
The FPGA sends an "auto-refresh" command to the SDRAM.
Ensure it is done regularly (the SDRAM data sheet will tell you the minimum refresh frequency).
The FPGA accesses each row "frequently".
Opening a row causes the "sense amplifier" in the SDRAM to get a copy of all the capacitor charges in that row. Then, when the row is closed, the earlier detected values are copied back to the capacitors, thus refreshing the data in the process.
FPGA XC3000 Family 2K Gates 100 Cells 100MHz 5V 44-Pin PLCC
FPGA XC3000 Family 2K Gates 100 Cells 100MHz 5V 84-Pin CPGA
FPGA Virtex-4 FX Family 56880 Cells 90nm Technology 1.2V 672-Pin FCBGA
FPGA Kintex UltraScale Family 424200 Cells 20nm Technology 0.95V 676-Pin FCBGA
Mechanical Sample IC