Date: Oct 11, 2022
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Among the founding members of the RISC-V International Foundation, many have already contributed to the development of the RISC-V ecosystem, such as SiFive, Crystal Heart, Syntacore, Codasip, Lattice, Microchip, etc., have launched RISC-V IP core solutions, and Loxin has also launched several RISC-V MCUs. Still, two senior founding members have made relatively few moves, namely Google and Qualcomm.
Despite its investment in SiFive, Qualcomm does not seem to be publicly invested in RISC-V development itself. Their former senior executive Travis Lanier mentioned at the 2019 RISC-V Summit that Qualcomm sees RISC-V as the second largest CPU ISA option besides Arm and has also used it in their embedded application processors, even saying, "In a few years, RISC-V will be on all of Qualcomm's cell phone SoCs", but that promise doesn't seem to have been fulfilled. He has gone to work as VP of marketing for Ventana Micro Systems, which builds high-performance RISC-V CPUs.
Google uses SiFive RISC-V processors in its TPUs, but Google itself does not seem to have any RISC-V-related products, and the CPUs in its own mobile SoCs are based on the Arm architecture. Is Google not interested in incorporating RISC-V into its product ecosystem? Of course not. Google has already started to promote the development of RISC-V from both software and hardware.
Google has been using its Tensor since the last generation of Pixel 6 products, and this year's Pixel 7 series also uses a new generation of Tensor G2. Still, as early as the previous Tensor generation, Google already used RISC-V.
Just as Apple also introduced T1 and T2 security chips in its Mac lineup, Google also chose to develop its standalone security chip, the Titan M2, which exists as a standalone security chip for Android smartphones and is used in the Pixel 6 series as well as the newly released Pixel 7 series.
Tensor G2 SoC / Google
In the functional partition of the Tensor SoC, we have already seen the presence of the security module, where the main use is Arm's TrustZone technology, which guarantees the general security processing of the entire SoC. Still, Google has prepared a security guarantee outside the Tensor SoC, which is Google's RISC-V processor, the Titan M2.
According to Google, the Titan M2 has higher speed and extra memory to more easily withstand advanced attacks. The Titan M2 has also passed the AVA_VAN.5 standard for vulnerability testing verification, can securely generate and store keys used to protect PINs and passwords, and works with the SoC security core to protect user data.
The name Titan may have come from Google's Titan Security Key, which was introduced in 2018. It was a physical USB key for tasks such as dual authentication, and the Titan Security Key then was still used with a secure chip from NXP.
As for the origin of the Titan, the M2 chip should be derived from OpenTitan, an open-source security chip design project that Google previously collaborated with LowRisc, another founding member of the RISC-V International Foundation, and a host of vendors such as Nuvoton Technology and Western Digital. As early as the end of 2020, Google announced that it was working with Nuvoton Technology to develop the first standalone OpenTitan chip product, which shows that Google designed the Titan M2 based on the OpenTitan project.
As a new architecture, RISC-V is getting better and better in terms of system support. Both Linux and major RTOS have noticed the potential of this ISA, and official and community porting work has been completed. However, RISC-V is still missing the support of another major open system ecosystem, Android.
If RISC-V could support this mobile system, it would drive the entire RISC-V ecosystem into high gear, and there is no shortage of such efforts within the RISC-V development community.
Recently, RISC-V for Android has finally reached a milestone. On October 1, the official AOSP community accepted the first RISC-V port-related patch, which means that RISC-V has finally entered the Android upstream ecosystem.
AOSP / Google
As we can see from the source code above, RISC-V has been added to the Android kernel headers and Arm and x86, so Google has identified the potential of Android On RISC-V. This way, with the joint collaboration of RISC-V International Foundation and Google, more ported code will be incorporated into AOSP after taking this first step.
Qualcomm and Google have not made RISC-V their primary goal but have chosen to continue polishing the Arm architecture. Their approach is very reasonable. Now Arm, especially under the mobile ecosystem, is still the mainstream.
They do not go to their design but choose to import more IP and design from other suppliers, not only in the wait and see, but also to promote the downstream market together to join and improve the RISC-V ecology because only in this way, the future of RISC-V will not be alone. The lower the risk of their formal entry will be.
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