Structure Analysis and Application of Simple Microcomputer Based on FPGA and VHDL

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Generally, people's understanding of the working principle and hardware structure of microcomputers comes from book knowledge. It is more difficult to deeply understand the functional characteristics of it. It is even more impossible to make a microcomputer with similar functions by yourself. With the wide application of programmable logic devices, it has brought great flexibility to the design of digital systems. Users can use FPGA (field programmable gate array) to develop a CPU with reduced instructions and the principle of microcomputers. Fully study the structure and structure to facilitate the design of related ASIC (Application Specific Integrated Circuit) in the future, and also be used in the teaching of computer principles.

1 Microcomputer structure and principle

Take a simplified microcomputer as an example, the simplified structure of the microcomputer.

1.1 Microcomputer structure

Microcomputer consists of PC (program counter), IR (instruction register), CON (control unit), MAR (storage address register), ROM (read only memory), A (accumulator), ALU (arithmetic logic unit), B ( Register), OUTREG (output register), DLEDDIS (digital tube dynamic scanning module) and DECL7S (display module) and so on.

L is the data loading control signal, E is the tri-state output strobe signal, clk is the clock signal, clr is the clear signal, Cp is the control PC plus 1 signal, S0-S3 is the control ALU for addition, subtraction or logic operation selection signal. All control, clock and clear signals are given by CON module, and CON module is controlled by external clock clkin and clear signal rst. The PC can be set to execute jump instructions. OUTREG can be cleared to facilitate multiple debugging. DLEDDIS and DECL7S are used to display the address and result on the nixie tube.

1.2 Principle of Microcomputer

Although this microcomputer can implement 16 instructions, this article does not extend the instructions, only 5 instructions as an example. LDA is to load data into accumulator A (operation code 0000); ADD is to perform addition operation (operation code 0001); SUB is to perform subtraction operation (operation code 0010); OUT is to output the result (operation code 1110); HLT is to stop (Operation code 1111).

After the program and data are loaded, when the clock signal and the clear signal are invalid from the outside, the CON module sends out the signal and control word, and starts to fetch and execute each instruction. If the control word sequence is ErLrS3S2S1SOEuLm LbEaLaEi LiCpEpLp, here Lr can be used as a write enable signal when the memory is RAM. Due to the integrated bus structure of the data bus and the address bus, the execution of one instruction requires 6 machine cycles, that is, the first 3 cycle fetching cycle and the last 3 cycle execution cycle. If ADD 0AH is executed, the machine code is 1AH (0001 1001). The first beat sends the PC content to the MAR, the control word is "0000 0001 00000010", that is, Ep and Lm are 1; the second beat sends the content in the corresponding address unit in the ROM to IR, and the upper 4 bits of IR are sent to CON, The control word is "1000 0000 0000 1000", that is, Er and Li are 1; the third beat adds 1 to the PC, the Cp in the control word is 1, and the rest is 0; the fourth beat sends the lower 4 bits of IR to MAR, Ei And Lm is 1; the fifth beat sends the contents of the ROM to the accumulator A, Er and La are 1; the sixth beat is the addition operation, Eu and La are 1, and S0-s3 is selected as the addition operation.

2 FPGA implementation

2.1 Bus mode

The bus mode refers to a microcomputer that implements the corresponding structure with FPGA strictly according to FIG. 1. This experiment uses Shanghai Hanghong's AEDK experiment box, FPGA chip is Altera's EPF10K20TC144-4, software uses QuartusII4.0, Max+plusII10.0 and synplifypr07.5, program design uses VHDL language.

There are a total of 11 sub-modules, and finally the component is used to form the total module. Take the design of the program counter module C-PC and the control module C_CON as an example to make a brief introduction.

When the tri-state output signal es is gated, that is, es="1", the PC can output, otherwise the output is in a high-impedance state. Data or address and bus-related sub-modules need to use three-state gates. Due to the use of three-state gates, it is best to use Quartus II software to compile, Max+plus II may not always pass.

Use synplify pro7.5 to observe the RTL (register transfer level) schematic diagram of the C_PC module, as shown in Figure 2. The integrated circuit is similar to a 4-bit binary counter, except for a three-state gate. With synplify pro7.5, not only can you observe the RTL circuit, but you can also observe the gate-level circuit junction to gain a deeper understanding of its internal structure.

The C_CON module is the most critical module because all control signals are sent by it. Since 6 machine ticks are required for command execution, each tick corresponds to a corresponding function, and the use of a state machine is an important way to achieve this highly efficient and reliable logic control. As shown in the following program, each state corresponds to a different control word, a total of 6 states.

The read-only memory module can use the LPM_FILE file of LPM_ROM, which is convenient for debugging different programs.