Research and Implementation of FPGA Configuration Method Based on DSP

In digital circuits, the system structure of FPGA+DSP is increasingly used. In order to reduce the volume and cost of this structure, passive parallel configuration is adopted for FPGA. After power-on, the DSP first loads its own program, and then acts as the main processor configuring the FPGA, reads the FPGA program from the FLASH chip, and loads the FPGA program according to the configuration timing. In terms of hardware design, innovatively adopts the way of sharing data bus between DSP, FPGA and FLASH. When DSP reads FPGA program from FLASH chip, FPGA can directly grab the data on the bus to complete loading. Practice has proved that this configuration method has a simple structure and stable operation, and has achieved miniaturization and low cost to a certain extent.

Introduction

In the field of signal processing, structural design based on FPGA+DSP has become an important direction of system development. With the wide application of the system design, the functions have become more abundant and the cost is getting lower. In some small-scale applications, the requirements for the system volume are getting higher and higher. Therefore, how to reduce the system volume at the hardware level has become the focus that must be considered. In addition to selecting highly integrated chips and a more compact circuit structure, optimizing the system's function implementation can reduce system volume at a higher level.

For the basic architecture of FPGA+DSP, the main structure of the DSP circuit module is a DSP chip and a FLASH chip that stores its program, which has a minimal structure and cannot be simplified. The FPGA circuit module is usually composed of an FPGA chip and a corresponding configuration chip. FPGA has multiple configuration methods. Different configuration methods require different chips. Therefore, the configuration method with a small number of chips can save the area of the circuit board to a certain extent.

Different manufacturers and different series of FPGA chips have different configuration methods. For Xilinx's Virtex-Ⅱ series FPGA, there are five configuration modes: active serial, active parallel, passive serial, passive parallel, and boundary scan. Among them, the boundary scan method can only write .bit files that are lost after power off, and cannot be used alone in the system; the configuration methods of active serial and active parallel require additional configuration chips, which is not conducive to streamlining the system; passive parallel and passive serial The configuration mode of the line depends on the microprocessor externally connected to the FPGA for configuration, and the DSP in the FPGA+DSP structure can just act as the microprocessor in the configuration circuit, so that the configuration chip and the JTAG circuit can be omitted. The module can reduce the system volume to a certain extent. This article chooses the passive parallel configuration method, because the higher configuration rate, this configuration method is of great significance in engineering practice.

1 Configuration method

1.1 Configuration file format

Configuring FPGA is to write the program files that have been integrated by the development tools into the FPGA chip at a certain timing. The Xilinx development environment can generate multiple file formats according to the user's choice, distinguished by different suffix names. Different file formats contain different information and have different uses. The most commonly used formats are .mcs format, .bit format and .bin format. Among them, .mcs files are used when programming the FPGA configuration chip, while .bit and .bin files are directly written to the FPGA. When used. The difference is that .bin contains only the most original configuration data, and the .bit file contains the most original configuration data, and also adds header redundancy information at the beginning, which contains the name of the current ISE project, Device model, compilation time, etc. This part of the information should not be programmed into the FPGA chip. Therefore, this article chooses to use the .bin file to configure the FPGA. Generally, the data of this configuration file starts with the hexadecimal synchronization character FF FF FF FF AA 99 55 66 specified by Xilinx, and ends after repeating the hexadecimal synchronization character 20 00 00 00 4 times.

Because the passive parallel configuration method saves the configuration chip, the FPGA program needs to be stored in the FLASH chip together with the DSP program. This article chooses to use the DSP of the AD company. The program file format used for flash programming is .ldr, and each line is composed of hexadecimal 0xXXXXXXXX data. Therefore, the format conversion of the .bin file used by the FPGA should be performed. Using Matlab tools, you can achieve this function. It should be noted that the .bin file is actually in the form of ASCII code, and it can be used only after it has been converted into the ASCII code. The .bin file is composed of several 2-bit hexadecimal data. For each data a(i), first extract the high and low bits, which can be done by Matlab functions floor(a(i)/16) and mod(a( i), 16) to achieve separately. Then the format code conversion is performed on the extracted data d, and the corresponding matlab program is as follows:

if(d<10)

d=d+48;

else

d=d+55;

end

1.2 Configuration pins

The pins related to FPGA configuration can be divided into 2 categories: dedicated pins and reusable pins. The function of the dedicated pin is fixed, and the reusable pin is used as the configuration pin during the configuration phase. After the configuration is completed, it can be configured as a general-purpose IO pin, or it can continue to be used as the configuration pin. The configuration pins are: asynchronous reset PROG_B, initialize INIT_B, configure clock CCLK, data input D0-D7, load success indication DONE, write signal RDWR_B, chip select signal CS_B, mode selection M0 ~ M2, busy indication BUSY (parallel loading and Only used when the clock rate is greater than 50 MHz). It should be noted that the usual microprocessor data format is little endian format, D0 bit is the least significant bit, and Xilinx FPGA uses the big endian format, when receiving program data, D0 bit is the most significant bit. The .bin file still uses the littIe endian format, and the most significant bit is D7, so the data needs to be converted into bit order. In this article, in order to simplify the operation, the sequence of data bits is directly converted on the hardware connection, that is, the D7 bit of the DSP is connected to the D0 bit of the FPGA, the D6 bit of the DSP is connected to the D1 bit of the FPGA, and so on.

1.3 Configuration process

The FPGA power-on configuration process can be roughly divided into four stages: power-on, initialization, data loading, and startup. The specific operations are as follows:

(1) Power on

The core power supply VCCint is greater than 2.5 V, and the pin supply voltage VCCO is greater than 1.0V, which can be completed after power-on.

(2) Initialization

After the power-on is completed, the external low-level PROG_B signal is input to reset the configuration register. At the same time, the FPGA pulls the INIT_B signal low to indicate that it is in the process of clearing the internal configuration register. When PROG_B is high, INIT_B still has to remain for a period of time until the configuration register is completely cleared. The PROG_B signal requires at least 300 ns, and there is no maximum limit. The PROG _B signal in this article is provided by the DSP.

(3) Data loading

On the rising edge of the INIT_B signal, the FPGA will sample its configuration mode pins M0~M2 to select different configuration methods. In this paper, the passive parallel mode requires M0~M2 value: 011. Then when the INIT_B signal is high, the configuration data loading starts. After the synchronization character is loaded, the real configuration logic data starts to be loaded. After the data is loaded and the correct CRC check is done twice, it starts to enter the FPGA startup phase, otherwise, the FPGA output INIT_B is low, and re-configure.

(4) Start

If the CRC check is correct, the FPGA pulls up the indication signal DONE, and then 4 CCLKs are needed to activate all the IO pins, enable and initialize the internal RAM, triggers, etc., and finally complete the FPGA startup process.

When generating the FPGA .bin file, you can set the clock CCLK frequency used when loading the FPGA. However, this frequency is only valid for the active loading mode. In the passive mode, the CCLK clock is supplied externally, regardless of this parameter.

2 Hardware implementation circuit

2.1 Hardware structure

This article selects the ADSP-TS101 chip produced by AD as the main processor for configuring FPGA. ADSP-TS101 is an extremely high-performance static superscalar processor that supports both floating-point and fixed-point processing. The maximum operating frequency is 300 MHz, the address range is 4 GB, and the maximum support is 16 MB of PROM. The 0x08000000～0xFFFFFFFF of the slave address is part of the external memory space, and can access independent peripheral devices, which can fully meet the addressing of off-chip programs. In order to complete the timing of configuring the FPGA, the DSP needs flexible and controllable pin signals. The four flag pin signals FLAG3 to FLAG0 of ADSP-TS101 allow bit signals to be transferred between ADSP-TS101 and other devices. Any flag pin can be used as input or output, and many instructions of ADSP-TS101 can use the input of the flag pin as the execution condition, which can efficiently communicate and synchronize between multiple processors and other interfaces. Therefore, you can connect these 4 pins to the FPGA to simulate the FPGA configuration timing.

The storage chip selects Spansion's high-performance FLASH chip S29JL064H, the minimum access period is 55 ns, which can be configured into 8M × 8 b storage mode. The configuration data of the Virtex-Ⅱ series FPGA includes configuration data frames and configuration register data. The configuration register data is 40×32 b, that is, 1 280 b. The configuration data frame will vary depending on the device. For XC2V1000 devices, The configuration data frame is 4 082 592 b, and the total configuration data is less than 4 Mb. Therefore, this memory chip can fully meet the storage of FPGA and DSP programs. For the division of FLASH storage space, the method of dividing into two is adopted, and the DSP and FPGA programs each occupy half of the space. That is, the 4 MB space from addresses 0x00000 to 0x3FFFFF is used to store the DSP program, and the remaining

4MB space 0x400000～0x7FFFFF stores FPGA program.

The schematic diagram of the hardware structure of the system is shown in Figure 1. The RD signal of the DSP serves as the configuration clock CCLK of the FPGA, the FLAG0 signal simulates the PROG_B signal of the FPGA, and FLAG1 and FLAG2 serve as the input of the DONE signal and the BUSY signal of the FPGA, respectively. This system uses DSP, FPGA, and FLASH to share the data bus during design, so when the DSP reads the FPGA loading data from the FLASH chip and appears on the bus, it can be directly grabbed by the FPGA to complete the FPGA program Normally loaded.

2.2 Working sequence

After the system is powered on, the DSP starts DMA channel 0, starting from FLASH address 0, and transfers a 256 word program block to the internal memory address 0x00～0xFF. Then, the DSP starts to execute the load core from 0x00, and the load core loads the subsequent application code and data into the internal memory after the address 0xFF. Finally, the loading core starts a 256-word DMA, making itself covered by the working program code. At this point, the DSP starts executing the work program from address 0x00. In the working program, first read the FPGA loading program from the FLASH memory and give the corresponding loading sequence to complete the loading of the FPGA program. The specific working sequence is shown in Figure 2.

3 Conclusion

With the increasing application of the FPGA+DSP system structure in the field of electronic design, on the premise of not adding other additional devices, relying on the DSP to simulate FPGA loading timing, the passive parallel configuration method is used for the FPGA. This method reduces the design redundancy to a certain extent, achieving miniaturization and low cost. Applied to the circuit system, the work is stable and reliable, flexible and efficient.