Realization and improved design of floating-point matrix multiplication based on Altera floating-point IP core

When the matrix data is loaded, the IP core divides the data into equal parts for vector multiplication.

Embedded computing, as an efficient operation method of the new generation computing system, is used in many high-performance fields, such as array signal processing, nuclear weapon simulation, and computational fluid dynamics. In these scientific calculations, a large number of floating-point matrix operations are required. The floating-point matrix operations that have been implemented so far are floating-point matrix multiplication processing units written directly in VHDL language. The key technology is the design of multiply-accumulate units. The performance of such designed hardware depends on the designer's programming level. In addition, FPGA manufacturers have also introduced a floating-point matrix computing IP core of a certain scale. Although this IP core uses the manufacturer's devices, and after professional debugging and hardware measurement, the performance is stable and better than handwritten code, but it can still be carried out. Improvements to further increase the speed of operations.

1 Altera floating-point matrix multiplication IP core principle

The floating-point matrix multiplication IP core ALTFP_MATRIX_MULT introduced by Altera is used in the environment of Quartus software version 9.1 and above, and can perform a certain-scale floating-point matrix multiplication operation, including A and B matrix data input, data floating-point multiplication and addition , The data cache and the sum of the four major outputs. Among them, the floating point multiplication and addition part can best reflect the performance of floating point calculation, and the surrounding control circuits and outputs affect the maximum clock frequency of the system and indirectly affect the overall performance of the system.

The principle of the entire matrix multiplication circuit is to input the single-channel data (the A and B matrix share the data line), generate the A and B matrix address signals through the controller, control the A matrix data output and the B matrix data output, and parallel the data The output is segmented to a floating-point multiply-add module for multiply-add operation, and then serially output to a buffer module, and then output to the floating-point addition module in parallel, and finally obtain the calculation result. It can be seen from its principle that there are still many improvements in data input and output.

2 Defects and improvement of IP core

2.1 There are defects

(1) Unbalance of input data bandwidth. When the data of matrix A and B is input, Altera’s IP core stores the A matrix data in the M144K Block RAM, and stores the B matrix data in the M9K Block RAM, resulting in the bandwidth of the A matrix data in the IP core being less than B The bandwidth of the matrix data and a certain number of register sets are required to make the bandwidth of the A matrix data match the bandwidth of the B matrix data. It can be seen that the storage of A and B matrix data is subject to device restrictions and storage constraints. At the same time, due to the different bandwidth of the input terminals (A and B matrix data) of the floating-point multiply-add module, the input of A matrix data requires additional processing time .

(2) The inconsistency of loading data. When the matrix data is loaded, the IP core divides the data into equal parts for vector multiplication. Due to the narrow storage bandwidth of matrix A, it requires 4 steps to register (determined by Blocks). Data B is loaded for calculation at the third cycle and sent to a FIFO for storage; matrix A is loaded at the sixth clock cycle. The second part performs the calculation of the second part, and finally when the 15th cycle is calculated, the first value of the matrix C can be calculated by floating point addition, and then the other value C11 of the matrix C is calculated. It can be seen from the above structure that after multiplying the segments, one FIFO is stored first, and then the next data FIFO is stored after being full, resulting in excessive waste of time.