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Processing of synchronous asynchronous clock domain signals in FPGAs

Date: Sep 27, 2021

Click Count: 63

The most commonly used constraints are IO pin location constraints and level amplitude constraints, which are well understood. In addition, is the clock network constraints. This is very important. For example, in your system, the clock of the driven circuit is 27M, then you need to add a constraint statement similar to the following in the constraint file

NET REF_CLK27M TNM_NET = REF_CLK27M_grp;

TIMESPEC TS_REF_CLK27M = PERIOD REF_CLK27M_grp : 37ns HIGH 50 %;

In this case, the tool will know when wiring that all the networks driven by this clock must meet the requirement of at least 27M speed with a duty cycle of 50%. It will be wired arbitrarily and there is a risk of very slow signal flip or very long delay and insufficient build time hold time, causing timing errors in practice. In general, more than a dozen megabytes of clock networks are best to add similar constraints on the clock will be fine, the tool will help you to add constraints to all the networks it drives.

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In addition, the common constraints are delay, skew, etc., you can download the specific Xilinx website to learn about Constains documentation.

We decompose the problem into two parts, the processing of signals from the synchronous clock domain and the processing of signals from the asynchronous clock domain. The former is much simpler, so we will discuss the former first, and then the latter.

1. The processing of synchronous clock domain signals

In general, in a fully synchronous design, if the signal comes from the same clock domain, the input of each module does not need to be hosted. As long as the establishment time, hold time constraint is satisfied, it can ensure that the input signal is already stable and can be sampled to get the correct value when the rising edge of the clock comes. However, if the module needs to use the jump edge of the input signal (e.g. frame synchronization signal), don't do this directly.

always @ (posedge inputs)

begin

...

end

Because this clock inputs is very problematic. If the begin ... end statements involve multiple D flip-flops, you can't guarantee that these flip-flop clock inputs will arrive at the same time (within a small acceptable range, to be exact). Therefore, if you write such a statement, the EDA tool will most likely report the clock skew 》 data delay, resulting in the establishment/hold time conflict. I have also written such a statement, when it was to do the frequency division, the influence of digital circuits learned in sophomore year, directly take the output of the counter to do the back of the module clock. The development tool is max+plusII, compile also passed, burned to the board to run up (estimated because the clock frequency is low, 6M), but then get QuartusII in the compile on the report clock skew 》 data delay. you may say that the crossover circuit is very common ah, crossover output how to use it. I have been using the method is to use the edge detection circuit, described in HDL language is probably as follows.

always @ (posedge Clk)

begin

inputs_reg 《= inputs;

if (inputs_reg == 1'b0 && inputs == 1'b1)

begin

...

end

...

end

This is the circuit for the upper jump edge detection, and so on for the lower jump edge circuit.

2. Handling of asynchronous clock domain signals

This issue is also discussed in terms of single signals and bus signals.

2.1 Handling of a single signal (e.g., control signal)

If this input signal comes from the asynchronous clock domain (such as the input from outside the FPGA chip), a synchronizer is generally used for synchronization. The most basic structure is two closely connected flip-flops, and the first beat synchronizes the input signal. The synchronized output may bring a conflict in the build/hold time and generate a sub-stable state. Another beat needs to be hosted to reduce (note that it is reduced) the effect of the sub-stability. This most basic structure is called a level synchronizer.

If we need to use the jump edge instead of the level and how to deal with it, remember the edge detection circuit in 1? After the level synchronizer, add another level flip-flop, and use the output of the second level flip-flop and the output of the third level flip-flop to operate. This structure is called an edge synchronizer.

always @ (posedge Clk)

begin

inputs_reg1 "= inputs;

inputs_reg2 "= inputs_reg1;

inputs_reg3 "= inputs_reg2;

if (inputs_reg2 == 1'b1 && inputs_reg3 == 1'b0)

begin

...

end

...

end

The above two synchronizers work well when the slow clock domain signal is synchronized into the fast clock domain, but the opposite may not work properly. As a very simple example, if the signal pulse being synchronized is only one fast clock cycle wide and lies between two adjacent jump edges of the slow clock, then it is not picked. This is where a pulse synchronizer is needed. This synchronizer is also composed of 3 flip-flops, and at the same time need to do some processing of the transmit signal, the specific structure you can search on the Internet.

2.2 Bus signal processing

If we simply use synchronizer for a group of signals coming from asynchronous clock domain, the chance of sub-stable state will be greatly increased for this group of signals as a whole. Based on this view, there are two ways to handle the bus signals.

If the group of signals only changes sequentially (e.g. the address of the memory), it can be converted to Gray code and then sent. Since the neighboring code words of Gray code only differ by one bit, the synchronizer mentioned above can work well.

But if the signal change is random (such as the memory data), this method will fail, then you can use the handshake or use FIFO or DPRAM for caching. RAM caching method in the burst data transmission advantage is more obvious, now a little high-grade FPGA have a lot of BlockRAM resources, and support the configuration of DPRAM or FIFO, this processing method is very good in the communication circuit. This processing method is very commonly used in communication circuits.

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