Date: Nov 27, 2020
Click Count: 2214
Today, I will introduce you to the simulation process of the ModelSim-Altera version. The article is relatively long and requires patience to read. If you have any questions, please feel free to communicate in the FPGAKey forum.
1. Establish a ModelSim-Altera working environment
1.1 release notes
ModelSim-Altera (OEM) version 6.4a
Quartus II version 9.0
This ModelSim version supports all Altera devices supported by Quartus II.
1.2 To automatically run EDA design input, synthesis, simulation, or timing analysis tools from the Quartus II software, you must specify the location of the executable file of the third-party EDA tool by clicking Options on the Tools menu and then clicking the EDA Tool Options option.
2. Build a project with ModelSim-Altera
2.1 If you want to perform timing simulation, you need to generate Verilog (.vo) or VHDL (.vho) output files.
a. Select EDA Tool Settings
b. Compile the design file with QuartusII
Note: If you have already compiled the design and want to regenerate .vo, .vho and .sdo (standard delayed output files), you only need to run Start EDA Netlist Writer. It can also be used to generate .vcd files.
If you want to perform power consumption estimation, make sure to select the appropriate parameters in the Settings dialog box under Simulator Settings.
2.2 Start Modelsim software, select the project directory: File—>Change Directory.
Tip: If you want to perform functional simulation, the project directory is the directory containing the design files;
If you want to perform timing simulation, the project directory must be set in the directory containing .vo, .vho, and .sdo.
2.3 Create a new working library:
a. File—>New—>Library, a dialog box for creating a new library appears
b. Under the Create option, select a new library and a logical mapping to it.
c. Enter the name of the library in Library Name
Tip: If you want to run Modelsim independently from QuartusII, the library file name must be work; if QuartusII automatically runs Modelsim, the name of the library is automatically named ModelSim_work and is located in the process directory of Quartus II.
3. Perform functional simulation with ModelSim-Altera
3.1 Compile Verilog or VHDL files and Test Bench files (if you use testbench)
a. Compile menu, click Compile.
b. Select the work library under the Library list
c. Select the required Verilog or VHDL file
Tip: If you choose .vo, .vho files as functional simulation, you must compile before the following operations.
d. Perform compilation
e. Repeat the above operation to compile the testbench file
f. Click done to finish.
3.2 Loading design:
a. In the Simulate menu, click Simulate. The Simulate dialog box appears
b. If you want to simulate a Verilog HDL design file, specify the ModelSim pre-compiled library
i. Click the Libraries tab
ii. In Search Libraries (-L), click Add to select the appropriate library
iii. Click OK to finish
c. In the Name list, click + to expand the work library, and select the top-level file to be simulated (usually testbench)
d. Click OK to finish
3.3 Perform functional simulation in ModelSim
4. Perform timing simulation with ModelSim-Altera
Important note: It is strongly recommended to set the Time scale to the femtosecond ps level during RAM simulation!
4.1 Compile Verilog or VHDL output files and testbench files in the same way as functional simulation.
4.2 If your design includes global reset or global power-on signals, and you have not done so, you can create these signals in Verilog or VDHL output files. Methods as below:
For Verilog, before the simulation, add the following code to the testbench file:
reg <device-wide reset>;
reg <device power up>;
<device power up> = 0;
#<time> <device power up> = 1;
For VHDL, run the following commands before simulation:
force /<design>/<entity>/<device power up> 0 0 ns
force <design>/<entity>/<device power up> 1 <time> ns
force /<design>/<entity>/<device-wide reset> 1 0 ns
Tip: <device-wide reset> is the name of the global reset signal, <device power up> is the global power-on signal, and <time> is a time value, which is between 0 and the actual start time of the simulation.
4.3 In the Simulate menu, click Simulate. The Simulate dialog box appears
4.4 If it is a simulated Verilog language, click the Verilog tab and fill in 0 in the Error Limit and Rejection Limit in Pulse Options.
4.5 If the simulation is a VHDL design, specify the .sdo standard delay file:
a. Click the SDF tab, click ADD
b. In the Add SDF Entry dialog box, click Browse, the Select SDF File dialog box appears
c. Select standard delayed output .sdo file
Tip: If you are using the test bench file as a design stimulus, then in the Apply to region box, starting from the top-level design file, point the path to the instance in the test bench
4.6 If the simulation is a Verilog design, specify the precompiled libraries (ModelSim pre-compiled libraries)
a. Click the Library tab, in Search Libraries (-L), click Add.
b. Specify the directory \<ModelSim-Altera install directory>\altera\verilog\<device family>\, click OK;
4.7 Click the Design tab, in the Name list, click + to expand the work library, and select the design entity corresponding to the standard delay output file, and click OK to complete.
4.8 If you want to simulate high-speed circuits (including HSSI, LVDS, PLLs, etc.), click the Others tab, enter +transport_int_delays +transport_path_delays in Other vsim options, and click OK to complete;
4.9 To directly generate .vcd (Value Change Dump File) files from ModelSim for PowerPlay Power Analyzer analysis in QuartusII, you can enter commands in ModelSim:
source <test bench or design instance name>_dump_all_vcd_nodes.TCL
4.10 The Tcl script file instructs ModelSim-Altera to monitor the output signal in the Tcl script file and write it into the .vcd file during the simulation.
4.11 Perform timing simulation in ModelSim-Altera.
Important note: It is strongly recommended to set the Time scale to the femtosecond ps level during RAM simulation!
This simulation process is the simplest. It does not require synthesis or placement and routing. You only need to write a good design file and import the testbench file directly into ModelSim to compile the simulation. At the same time, for Verilog language, you need to select the corresponding RTL simulation library. The main RTL simulation libraries are as follows:
★ Post-synthesis simulation (functional simulation)
Tip: This process can only be carried out after synthesis. What is needed is the Verilog output file, not the design file! At the same time, for the simulation library, the gate-level simulation library is used instead of the RTL simulation library (that is, the simulation library of the device corresponding series). The commonly used gate-level and compiled simulation libraries are as follows:
1. Steps: select directory—>build a library—>compile—>simulation
1.1 The directory is selected under the EDA netlist directory generated by QuartusII, the path: <project directory>\simulation\modelsim, this is to facilitate the call of files;
1.2 Build a library in this directory. To work independently of QuartusII, the library name must be work;
1.3 Compile the file. Generally speaking, testbench is used, so you can use the (.vo+.vt) combination method for simulation. .vo is the Verilog output file, and .vt is the Verilog test file; if it is VHDL, it is .vho and .vht respectively. The best compilation order is to output files (.vo, .vho files) first, and then test files (.vt, vht files)
1.4 Start the simulation. If you use related LPM, MF, or IP, you must add the corresponding pre-compiled simulation library. Click Add in Library—>Search Libraries (-L). Then select the simulation top-level file under Design—>Name—>work. If there is a testbench, generally select testbench.
2. About the testbench file automatically generated by QuartusII
The testbench file automatically generated by QuartusII contains a global register each, which contains a statement @eachvec, remember to comment it out, otherwise, the simulation may fail because it is not triggered.
☆Automatically generate simulation netlist in QuartusII: Assignments->EDA Tool Settings
☆TsetBench is automatically generated in QuartusII: Processing->Start->Start Test Bench Template Write
★Gate-level simulation (timing simulation)
ModelSim's timing simulation is the same as functional simulation, but the following differences should be noted:
1. If it includes a global reset or global power-on signal, it needs to be processed accordingly, see the previous text for details;
2. When simulating the Verilog program, there is no need to add the .sdo file. Verilog automatically calls the .sdo file by adding a pre-compiled library. At the same time, enter 0 in Error Limit and Rejection Limit in Pulse Options;
3. When performing timing simulation on the VHDL file, you must add the .sdo file and assign it to the corresponding module in the testbench in Apply to the region;
In testbench, each continuous signal is best described with an independent always statement, otherwise, conflicts may occur and simulation errors may occur.
Use QuartusII to automatically run ModelSim simulation
First, note a few points:
1. Remember that the path cannot contain non-letter type text when using Modelsim to simulate.
2. When you want to simulate again, make sure that the ModelSim program of the previous simulation has exited, otherwise, an error similar to the following will be reported!
3. The reason for the above error may also be the use of an IP core that does not support RTL level simulation, but it does not affect timing simulation.
4. When using a wave file to generate a testbench file, it is best to only have input information and not include any output information;
Here is how to do it:
1. Configure NativeLink
1.1 Enter EDA Tool Settings, select Simulation in EDA Tool Settings, as shown in the figure:
1.2 The configuration on the right side of the simulation dialog box is as follows (Verilog):
If you want to run gate-level simulation automatically after compilation, you can check Run gate-level simulation… after compilation.
1.3 Compile the testbench file
Click Test Benches in NativeLink settings, and click New in the dialog box that appears, and the following dialog box appears:
You can fill in a name in Testbench name, which is the alias of the current Testbench file;
The top-level module in the test bench is filled with the top-level module to be simulated in Testbench;
Design instance name in test bench: Fill in the instantiation name of the source program of the top-level module in the Testbench.
Add the corresponding Testbench file in the Test bench files bar, click Add to add, and then click OK to complete the configuration.
2. Run the simulation
If you want to simulate manually, you can also call Modelsim in QuartusII, as follows:
Among them, RTL Simulation is a register transfer level simulation. It is an idealized simulation and does not contain any delay information. It is usually used for functional testing and is also called pre-simulation or functional simulation;
Gate-Level Simulation is a gate-level simulation, usually called post-simulation or timing simulation. It contains delay information such as logic circuits, layout, and routing, and is a simulation of real circuit conditions. To simulate the gate-level simulation, it needs to be performed after Fitter.
3. Generate Testbench
There are two ways to generate Testbench from QuartusII:
(1) Export from the wave file, the method is as follows:
Open the waveform simulation file, edit the input information,
Click File—>Export to export directly.
(2) You can also use QuartusII to generate a Testbench template, and then enter the test information yourself.
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