Meeting design challenges in the era of wearable devices

Wearable electronic devices present unprecedented challenges for design engineers—design engineers need to create smart, compact, and versatile products without dedicated chipsets or standardized architectures. Due to the lack of dedicated chipsets (standardized architecture), design engineers need to use devices and interconnect technologies designed for mobile and handheld applications in wearable products.

How to bridge the digital and analog “gap” between two unrelated devices is not a small design challenge, but it is even more difficult for wearable devices with strict space and power consumption restrictions. At the same time, the fast-growing market requires design engineers to keep up with the changing needs of consumers, quickly upgrade the functions of existing products and launch new products.

This article will study the design challenges of wearable products and explore how to use programmable logic products to solve these problems. The design examples in this article are intended to illustrate how to apply special programmable devices to the following three aspects:

Expand

Use additional logic and custom functions to extend the functionality and service life of existing ASICs and ASSPs.

upgrade

Use programmable logic products to implement new protocols and standards, and to bridge interconnections between incompatible components to upgrade the design of wearable devices.

Innovation. No need to invest a lot of time and expense in ASIC development, use the flexible platform provided by programmable logic products to achieve advanced functions or new features.

Wearable devices bring unprecedented design challenges

Wearable electronic products are in the early stages of development, and the technology is not yet mature. Just like the evolution of life on the earth, technological innovation like the Cambrian life explosion will occur. It is foreseeable that at least in the next 3 to 5 years, there will be a variety of products and trial releases, forming a market with the following characteristics:

● The market is rapidly innovating, and consumer demand is changing rapidly at the same rate;

●The emergence and development of brand-new products sometimes disappear eventually;

● There are many competing products, but failed to form a standard feature set;

● Even if there are only a few standardized architectures or interface standards.

During this period of vigorous development, the development of semiconductor devices that products rely on will not keep up with the speed of iterative updates of the products themselves. Because IC development usually takes 12 to 18 months, if manufacturers insist on developing ASICs for the wearable market, it is likely that the products will not be fully functional or outdated when they go to market.

Without an application-optimized microcontroller (MCU) and ASSP, wearable device design engineers must use general-purpose MCUs or use highly integrated devices from more mature applications, such as smartphones, tablets, and other handheld/mobile devices In the device. Both of the above methods provide design engineers with a highly integrated embedded computing platform without the need to invest a lot of time and cost in developing special devices. Not only that, many development tools and application software support most of these off-the-shelf devices, which is an additional advantage.

Although the use of such mobile devices in wearable applications can provide many advantages, design engineers still face many challenges during the design process. The first challenge is that the wearable device market is changing very fast. The embedded computing devices used in the initial product may not have the relevant interfaces and I/O functions to support all the new functions required by the next generation of products. In order to keep up with the pace of market changes, design engineers must add expansion circuits to product designs or find more powerful MCU/ASSP.

The second challenge is also a more general problem—most of these embedded computing devices do not have the relevant interfaces for various types of sensors, displays, and other I/O devices most commonly used in wearable applications. In some cases, the interface of the sensor or display screen does not match the data bus of the system, or is incompatible with the format used by the system application processor, which will lead to the occurrence of "Digital Disconnect" (Figure 1).

For example, the Sub-LVDS interface commonly used in CMOS image sensors uses a different data frame format than the CSI-2 interface used by many common application processors (Figure 1). In addition, the device interface may also have a different number of serial channels. Another cause of "digital breakage" is that many general-purpose MCUs have GPIO and other parallel interfaces, which must be converted into a serial format used by most sensors and displays today. In addition, the number of pins in the compact package MCU used in wearable applications is too small, limiting the number of devices that can be directly accessed.

There is also a "functional divide" between the interfaces supported by the application processor and the interfaces required by many sensors and output devices. A simple example is that a wearable device can realize infrared remote control of a TV or other electronic products. In this case, the LED driving capability that most MCUs do not have has become a "functional gap" between the application processor and infrared (IR) LEDs.

The IR encoder is a purely digital function, at least in theory it can be implemented by the application processor of the MCU. But in many cases, this is not the most ideal solution, because the real-time encoding requires more processor resources than the system can save. In addition, the extra time that the application processor spends on coding tasks will cause too much limited system power consumption, so it is best to use hardware.

FPGA-based solutions

Now, FPGAs can provide cost-effective ways to bridge between interfaces and add new features to existing devices and shorten design cycles. The early programmable logic devices were relatively expensive, and the power consumption was amazing, so they were often used as prototyping tools and "glued" components for the first-generation design or small batch products.

After entering the 21st century, the development of deep sub-micron technology and new architecture has driven the implementation of new FPGAs with enhanced performance and versatility, and significantly reduced costs and power consumption. This allows current FPGAs to play multiple roles in wearable electronic devices.

Of course, FPGAs continue to play a role in their traditional applications, such as providing "glue" logic, implementing basic functions, including providing additional logic units (gate circuits, latches, flip-flops, etc.), adding input signal conditioning ( Level translation, Schmitt triggers and inverters), as well as providing expansion paths for existing host processor I/O interconnects.

FPGA can also be used to implement the more complex functions mentioned above. The simplest form is to provide a bridge function. As shown in Figure 2, FPGA can solve the problem of bridging between the sensor Sub-LVDS interface shown in Figure 1 and the CSI-2I/O bus of the application processor.

FPGA-based bridges are also often used in serial/parallel conversion applications. Figure 3 shows how a programmable logic device converts the application processor's standard parallel bus into the serial format of the most commonly used MIPIDSI interface for wearable device displays. In this application, FPGA is responsible for the following functions:

Redefine the LVDS output format of the image sensor to match the number of channels and data rates supported by the application processor;

Transmit the sensor's data clock signal to the application processor to achieve any required signal encoding;

Use programmable logic instead of the application processor's limited machine cycle to implement the screen refresh action.

The bridge function can also be used as a building block for larger FPGA-based system elements, such as implementing the dual-input bridge/processor in Figure 4, which will receive CSI-2 serial data streams from 2 independent image sensors and Its processing is a single CSI-2 or parallel or HiSPI output. According to the selected algorithm, the independent data stream can be color adjusted or compensated in time or space to generate a single 3D image, or it can be displayed separately at different positions on the screen coordinate space to produce a picture-in-picture effect.

FPGA helps energy saving technology

In the previous examples, the main purpose of the design was to enhance the interconnection or function of the application processor itself. But these FPGA-based solutions also provide another important benefit: the MCU or ASSP does not need to perform one or more computationally intensive tasks at the same time, thereby saving limited processor resources.

However, in many cases, the reduction in power consumption of these designs is more important. For example, the design in Figure 3 includes a hardware screen refresh function that consumes only a fraction of the power required by traditional processor cores. Similarly, some small-size, low-power FPGA logic devices in FIG. 4 perform image processing tasks independently of the host processor, which allows the host processor to be in an energy-saving sleep mode most of the time.

Many applications discussed below use this energy-saving design method and are suitable for most wearable applications with low power consumption requirements.

FPGA can accelerate design upgrade and new design implementation

Wearable electronic devices are developing rapidly, and each generation of new products adds more functions and features than the previous generation. In these applications, small-size, low-cost FPGAs are often used to extend the basic functions of wearable device application processors.

Many modern microcontrollers have powerful computing capabilities to manage sensors and process the data they generate, and integrate it with other data streams. However, using a microcontroller to complete these tasks will consume valuable I/O resources and require the processor to be in a working state for a long time, which will affect the battery life.

FPGAs can be used to create semi-autonomous I/O modules that can collect data from multiple sensors and complete other advanced functions without processor intervention. The "always online" low-power pedometer uses a 3-axis accelerometer as the main sensor, records the wearer's steps, calculates the distance traveled, and measures the calories burned and the time of movement.

In this design, some FPGA logic units are configured as a bridge between the I2C interface of the accelerometer and the SPI/O bus of the application processor. Other FPGA function blocks are used to configure and manage the accelerometer. Programmable logic can also be used to process raw accelerometer data, using statistical filtering and step detection algorithms for noisy data streams. Another part of the function of FPGA is to cache the obtained steps and acceleration information until the host processor wakes up from low-power sleep state and collects these data. Using programmable logic cores to perform these computationally intensive tasks can keep the application processor in sleep mode for a long time, which helps reduce the power consumption of the pedometer. Implementing these functions through FPGAs also allows designers to use simpler, lower-power microcontrollers without affecting the performance and accuracy of the pedometer.

FPGAs provide scalable solutions

Another advantage of using FPGA is that FPGA manufacturers usually provide a series of similar devices, each device has a different combination of programmable logic and I/O. Using FPGAs as a supplement or replacement for ASICs, design engineers can choose the number of logic gates they currently need and develop solutions of appropriate size.

Because devices of the same FPGA family share parameters, features, and development resources, various logic densities and I/O configuration choices allow manufacturers to adopt a "buy when you upgrade" strategy to add new features to existing designs, or reorganize Existing functions to develop new products. Because the same series of devices share a common tool chain and IP library, design engineers can quickly upgrade and follow-up design from the idea to the product to the market.

To sum up

The lack of a standard architecture, feature set, and dedicated chips for wearable devices has brought unprecedented challenges to mobile consumer electronics designs that are already faced with tight cost, power consumption, and size constraints. This article describes how FPGAs can help design engineers solve the above problems through some simple methods, such as: bridging the interface between existing microcontrollers, sensors, displays, etc., and adding new interconnections to existing microcontrollers and ASSPs And functions, and in some cases provides an alternative to ASIC or SoC.

Due to its flexibility, scalability, and lower solution cost, FPGAs have redefined the traditional design cycle for many types of products and provided design engineers with many advantages over traditional ASICs.