Date: Aug 30, 2021
Click Count: 85
All clocks generated by the PS clock subsystem come from one of three programmable PLLs: CPU, DDR, and I/O. Each of these PLLs is associated with a clock in the CPU, DDR, and peripheral subsystems.
The main components of the clocking subsystem are shown in the figure.
PS Clock System Block Diagram
During normal operation, the PLL is enabled and driven by the PS_CLK clock pin; in bypass mode, the clock signal on the PS_CLK pin sources the various clock generators instead of the phase-locked loop.
When the PS_POR reset signal is disabled, the PLL bypass boot mode pin is sampled and selected between PLL bypass and PLL enable for all three PLLs.
Bypass mode runs the system significantly slower than normal mode, but is useful for low-power applications and debugging, where the bypass mode and output frequency of each PLL can be controlled individually by software after the boot process and while user code is executing.
The clock generation path includes interference-free multiplexers and interference-free clock gates to support dynamic clock control.
3 Programmable PLLs
A single external reference clock input for all three PLLs, as follows.
ARM PLL: Recommended clock source for CPU and interconnect
DDR PLL: Recommended clock for DDR DRAM controller and AXI_HP interface
I/O PLL: Recommended clock for I/O peripherals
Separate PLL bypass control and frequency programming
Shared bandgap reference voltage circuit for VCO
Six-bit programmable divider
Dynamic switching for most clock circuits
PL's four clock generators
The clock subsystem is an integral part of the PS and is only reset when the entire system is reset. When this happens, all registers controlling the clock modules return to their reset values.
The following diagram shows the clock network and associated domains from a system perspective
A version of the CPU clock is used for most internal clocks, and the asynchronous DMA peripheral request interface between DMAC and PL is not shown in the figure. In addition, the PL AXI channels (AXI_HP, AXI_ACP, and AXI_GP) have an asynchronous interface between the PS and PL, with synchronization of the clock domain crossover occurring within the PS.
Therefore, PL provides the interface clock for PS, and each of the above interfaces can use a unique clock in PL.
Clock generation subsystem helps clock disabling and frequency control that affects power consumption, PLL power consumption is directly related to the PLL output frequency, using a lower PLL output frequency can reduce power consumption, if one or two of them, can also reduce power without PLL.
For example, if all clock generators can be driven by the DDR PLL, the ARM and I/O PLLs can be disabled to reduce power consumption, and the DDR PLL is the only unit that can drive all clock generators.
Each clock can be individually disabled when not in use, and in some cases, individual subsystems include additional clock disabling and other power reduction features.
Central Interconnect Clock Disable
The CPU clock for the central interconnect (CPU_2x and CPU_1x) can be stopped by setting the TOPSW_CLK_CTRL  bit to 1. With this bit set, the clock controller waits for the L2 cache and the AXI interface of the SCU to become idle and the FPGAIDLEN signal from the PL to assert before turning off the clock for the central interconnect.
For other interfaces, the system software must ensure that the interface is idle before disabling the interconnect clock, and the clock will be re-enabled once the PS detects traffic on the L2 cache or SCU, or the FPGAIDLEN is de-asserted.