Date: Nov 25, 2020
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I have introduced Xilinx Spartan-7 andCoolRunner-II CPLD series to you earlier. Many friends suggested that I talk about Xilinx Zynq. Because Xilinx Zynq includes three series, for the convenience of introduction, I will introduce the Zynq 7000 series first. Xilinx Zynq 7000 is an expandable processing platform based on APSOC. Its essential feature is to integrate a dual-core ARM Cortex-A9 processor and a programmable FPGA chip into a system-on-chip. Before proceeding with the detailed description of Zynq 7000, first introduce the high-level model of the architecture.
Usually, the ARM processor and various storage peripheral resources are called the processing system, and the FPGA part is called the programmable logic. ARM Cortex-A9 is an application-level processor that supports operations similar to the Linux operating system. The Xilinx7 architecture adopted by the FPGA implements the industry-standard AXI interface, which forms an efficient coupling between ARM and FPGA, reduces the additional power consumption of discrete chips, and not only achieves high-bandwidth, low-latency connections but also brings The physical size and production cost are reduced.
It is worth mentioning that the PL part of Xilinx Zynq 7000 can be configured with a soft processor MicroBlaze. Micro-Blaze is a combination of programmable logic units, that is, the implementation and deployment of a MicroBlaze are equivalent to an ordinary IP core in FPGA. The soft processor can work with ARM to coordinate specific underlying functions and the cooperation between the system and separate some less demanding tasks from the ARM Cortex-A9 processor to improve the performance of the system.
The PL part of Zynq 7000 is used to realize the subsystem of high-speed logic operation and parallel data stream processing is very ideal, and the PS part supports software control or operating system. This means that based on this platform, most system designs can be divided into software and hardware-based functions so that both PS and PL can play their respective advantages so that the entire system can show the best performance.
Zynq 7000 system-on-chip internal architecture diagram
Xilinx Zynq7010/20 development board
Xilinx Zynq development board
The resources of the processing system include
Application Processing Unit (APU): Dual-core ARM Cortex-A9 processor with a maximum operating frequency of 1GHz. Anyone of the two cores contains a first-level cache (divided into two parts: data and instructions, each of which is 32KB), and a memory management unit (MMU, which translates between virtual addresses and physical addresses). Also, the two cores share a 512KB secondary cache to store instructions and data. Other system resources also include NEONTM media processing engine and floating-point unit (FPU), on-chip memory (OCM), consistency control unit (SCU), interrupt controller, etc. The SCU forms a bridge connection between the ARM core and the secondary cache and OCM memory and is also partly responsible for docking with the PL.
AXI interface, the main connection form between PS and PL part in Zynq is the AXI interface.
The memory interface supports 16-bit/32-bit wide DDR3, DDR2, and four-wire SPI controllers.
I/O peripheral interfaces, including multiplexed input/output pins (MIO), extended MIO (EMIO, realized by sharing PL I/O resources), standard communication interfaces, and general-purpose input/output pins (GPIO). Besides, there are Ethernet controllers (supporting 10Mbps, 100Mbps, and 1Gbps modes), USB controllers, SD/SDIO controllers, 4-wire SPI controllers, CAN controllers, UART controllers, and I2C controllers.
The resources of the PL part mainly include
General FPGA logic part. It mainly includes logic slices and configurable logic blocks, as well as input/output blocks for interfaces.
XADC block. This is a dedicated analog-to-digital converter (Analogue to Digital Converter, ADC) mixed-signal hardware, with two independent 12-bit ADCs, each of which can sample externally input analog signals at a sampling frequency of 1Msps. The control of XADC is realized by the PS-XADC interface control block located in the PS, and the PS-XADC control block itself can be programmed and controlled by the APU.
Clock: PL receives four independent clock inputs from PS, and can also generate and distribute its clock signals that are not related to PS. This independent PL resource is equivalent to that in the 7 series FPGA.
FPGA Spartan-3 Family 400K Gates 8064 Cells 90nm Technology 1.2V Automotive 208-Pin PQFP
FPGA XA Spartan-3A Family 400K Gates 8064 Cells 667MHz 90nm Technology 1.2V Automotive 256-Pin FTBGA
FPGA XA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V Automotive 256-Pin FTBGA
FPGA XC4000X Family 10K Gates 950 Cells 0.35um Technology 3.3V 208-Pin PQFP