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Introduction to the Zynq-7000 Series DMA Controllers

Date: Jun 28, 2021

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Introduction to the DMA Controller

The DMA controller (DMAC) uses a 64-bit AXI host interface running at the CPU_2x clock rate to perform DMA data transfers to and from system memory and PL peripherals. The transfers are controlled by a DMA instruction execution engine that runs on a small instruction set that provides a flexible method for specifying DMA transfers. The DMA engine operates on a small instruction set that provides a flexible method of specifying DMA transfers, which provides greater flexibility than the DMA controller method.

The DMA engine program code is written by software to an area of system memory that is accessed by the controller using its AXI host interface, and the DMA engine instruction set includes instructions for DMA transfers and management instructions for the control system.

The controller can be configured with up to eight DMA channels, each corresponding to a thread running on the DMA engine processor. When a DMA thread executes a load or store instruction, the DMA engine pushes the memory request to the associated read or write queue.

The DMA controller uses these queues to buffer AXI read/write transactions, and the controller contains a multi-channel FIFO (MFIFO) for storing data during DMA transfers.

Program code running on the DMA engine processor treats the MFIFO as containing a set of parallel FIFOs of variable depth for DMA read and write transactions, and the program code must manage the MFIFO so that the total depth of all DMA FIFOs does not exceed 1024 bytes of MFIFO.

DMAC is capable of moving large amounts of data without processor intervention, and the source and target memory can be located anywhere in the system (PS or PL), and DMAC's memory mapping includes DDR, OCM, linearly addressed Quad-SPI read memory, SMC memory, and PL peripherals or connected to the M_GP_AXI interface. Memory.

The flow control method for PS memory transfers uses AXI interconnects, access to PL peripherals can use AXI flow control or DMAC's PL peripheral request interface, there is no peripheral request interface to PS I/O peripherals (IOP), and for PL peripheral AXI transactions, software running on the CPU uses interrupts or For PL peripheral AXI transactions, software running on the CPU uses programmed IO methods using interrupts or status polling.

The controller has two sets of control and status registers, one accessible in safe mode and the other accessible in non-safe mode. Software accesses these registers through the controller's 32-bit APB slave interface, and the entire controller operates in either safe or non-safe mode; there is no channel-based mode mixing, and safe configuration changes are controlled by the slcr register and require a controller reset to take effect.

DMA Controller Features

The DMA controller provides.

1.DMA engine processor with a flexible instruction set for DMA transfers.

  • Flexible scatter-aggregate memory transfers

  • Full control of source and destination addressing

  • Defined AXI transaction attributes

  • Management of byte streams

2.Eight cache lines, each four words wide

3.Eight concurrent DMA channel threads

  • Allows multiple threads to execute in parallel

  • Issuing up to eight read and up to eight write commands for AXI transactions

4.Eight interrupts to PS interrupt controller and PL

5.Eight events in the DMA engine program code

6.128 (64-bit) word MFIFO for buffering data written or read by the controller during transfers


  • Dedicated APB slave interface for secure register access

  • Entire controller configured as secure or non-secure

8.Memory-to-memory DMA transfers

9.Four PL peripheral request interfaces to manage flow control to and from PL logic

  • Each interface accepts up to four active requests

DMA System View

A system view of the DMA module is shown in the figure


DMA Controller Summary

DMA (Direct Memory Access) is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on the CPU's heavy interrupt load, and is widely used.

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