Introduction to FPGA basic knowledge

FPGA (Field Programmable Gate Array) is a field programmable gate array. It is a product of further development on the basis of programmable devices such as PLA, PAL, GAL, CPLD and so on. It is a semi-custom circuit in the field of application specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gates of the original programmable devices.

1. Introduction to FPGA

FPGAs are commonly used to implement digital circuit modules. Users can reconfigure the logic modules and I/O modules inside the FPGA to meet user needs. It also has the characteristics of static repeatable programming and dynamic reconfiguration in the system, so that the functions of the hardware can be modified by programming like software. It is no exaggeration to say that FPGA can complete the functions of any digital device, from simple 74 circuits to high-performance CPUs, which can be implemented with FPGA. FPGA is like a piece of blank paper or a pile of wood. Engineers can freely design a digital system through traditional schematic input methods or hardware description languages.

2. History of FPGA development

The development history of FPGA is shown in the figure below. Compared with PROM, PAL/GAL, CPLD, FPGA scale is larger and performance is higher.

The mainstream FPGA chip manufacturers include Xilinx, Altera, Lattice, and Microsemi, of which the total market share of the first two has reached 88%. At present, all mainstream FPGA manufacturers are American manufacturers. The domestic FPGA has been developed at least 20 years later than the United States. It is still in the growth stage, limited to the low-end, and has no mature application in the communications market.

In December 2015, Intel bought Altera for $16.7 billion. Altera formulated the product roadmap for Intel processor and FPGA integration shortly after it was acquired. The advantage of the integration of these two products is that they can provide innovative heterogeneous multi-core architectures, adapt to the needs of new markets such as artificial intelligence, and can significantly reduce power consumption.

FPGA has very mature and extensive applications in the aerospace, military, and telecommunications fields. Taking the telecommunications field as an example, at the stage of telecommunications equipment integration, FPGAs are parsed by application network protocols and interface converted due to their programming flexibility and high performance.

In the NFV (NetworkFunction Virtualization stage), FPGA achieves a fivefold performance improvement of the network element data plane based on general-purpose servers and hypervisors, and can be managed and arranged by the general Openstack framework.

In the cloud era, FPGAs have been used as basic IaaS resources to provide development services and acceleration services in public clouds. AWS, Huawei, and BAT all have similar general services.

As of now, Intel's Stratix 10 device has been successfully used in the Brainwave project of Microsoft's real-time artificial intelligence cloud platform.

3. Recent development of two mainstream FPGA companies

Xilinx focused on chip leadership and rich acceleration solutions, and gained support from mainstream cloud platforms through its open strategy, establishing its leading position in the data center. Its UltraScale+ series of FPGAs have been leading friends for more than a year, making it a leader in cloud platform competition. Its VU9P devices are widely used in cloud computing platforms of multiple companies including AWS, Baidu, Ali, Tencent, and Huawei.

In order to meet the increasing performance requirements of FPGA chips in the accelerator field, Xilinx has released the next-generation ACAP chip architecture for data centers and launched 7nm Everest devices. This device is no longer a traditional FPGA, it integrates ARM, DSP, Math Engine processor array and other cores, and will be mass-produced in 2019. Compared with VU9P, Everest supports AI processing performance that can be increased by 20 times.

Intel provides a full-stack solution from hardware to platform to application. It does not open the hardware and platform design to avoid ecological fragmentation. The investment is huge but the progress is slow.

FPGA has some technical difficulties in the actual application of the data center server market, including the following aspects:

1. Higher programming threshold: The hardware description language is different from the software development language, which requires developers to have a deeper understanding of the underlying hardware; therefore, talent has become an important factor limiting FPGA applications. It is understood that the current domestic staff engaged in FPGA development is initially estimated to be more than 20,000.

2. Difficult integration: FPGA development and application require the coordination of software and hardware, including system modeling using high-level languages, hardware code (circuit) design, hardware code simulation, joint debugging of the underlying driver software and hardware logic, etc.

3. The development cycle is longer than that of software: hardware development is more complicated than software development, and the debugging cycle is also lengthened.

4. It is difficult to obtain an independent logical IP.

4. The overall structure of FPGA

The FPGA architecture mainly includes four parts: Configurable Logic Block (CLB), IOB (Input Output Block), Interconnect and other embedded units.

CLB is the basic logic unit of FPGA. The actual number and characteristics will vary from device to device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, several selection circuits (multiplexer, etc.) and flip-flops. The switch matrix is highly flexible and can be configured to handle combinational logic, shift registers, or RAM.

FPGA can support many kinds of I/O standards, so it can provide ideal interface bridge for system design. The I/O in the FPGA is grouped by bank, and each bank can independently support different I/O standards. At present, the most advanced FPGA provides more than ten I/O banks, which can provide flexible I/O support.

CLB provides logic performance, and flexible interconnect wiring is responsible for passing signals between CLB and I/O. There are several types of routing, from designing specifically to implement CLB interconnects (short-line resources), to high-speed horizontal and vertical long-lines within the device (long-line resources), to global low-skew routing of clocks and other global signals (global dedicated Wiring resources). Generally, the design software of various manufacturers hides the interconnection and wiring task, which is not visible to users at all, thereby greatly reducing the design complexity.

The embedded hard core unit includes RAM, DSP, DCM (Digital Clock Management Module) and other specific interface hard cores, etc. The internal structure of the FPGA device is as follows.

In general, the larger the device model number, the larger the scale of logic resources that the device can provide. In the selection of FPGA devices, users need to refer to this table, according to business requirements for logic resources (CLB), internal BlockRAM, interface (high-speed Serdes logarithm), digital signal processing (DSP hard core number), and future expansion. , Comprehensively consider the most suitable logic device for the project.

5. FPGA development process

The design process of FPGA is the process of developing FPGA chips using EDA development software and programming tools. The development process of FPGA is generally shown in the following figure, including the main steps of function definition/device selection, design input, functional simulation, logic synthesis, layout and implementation, programming and debugging.

1. Function definition/device selection：Before the FPGA design project starts, there must be a system function definition and a module division. In addition, according to the task requirements, such as the system function and complexity, the working speed and device resources , Cost, and wiring can be weighed, select the appropriate design and the appropriate device type.

2. Design input: Design input refers to using a hardware description language to express the designed system or circuit in code. The most commonly used hardware description language is Verilog HDL.

3. Functional simulation: Functional simulation refers to verifying the logic function of the circuit designed by the user before logic synthesis. Before the simulation, you need to build a test platform and prepare the test incentives. The simulation results will generate a report file and output signal waveform, from which you can observe the signal changes of each node. If an error is found, it returns to design modification logic design. Commonly used simulation tools are ModelSim from Model Tech and VCS from Sysnopsys.

4. Logic synthesis: The so-called synthesis is to transform the description of the higher level of abstraction into the description of the lower level. Comprehensive optimization optimizes the logical connections generated according to the goals and requirements to planarize the hierarchical design for FPGA placement and routing software. At the current level, comprehensive optimization refers to compiling design inputs into a logical connection netlist composed of basic logic units such as AND gates, OR gates, NOT gates, RAMs, and flip-flops, rather than real gate-level circuits.

Real and specific gate-level circuits need to be generated based on the standard gate-level structure netlist generated after synthesis by using the layout and routing functions of FPGA manufacturers. In order to be converted into a standard gate-level structure netlist, the HDL program must be written in accordance with the style required by a specific synthesizer. Commonly used synthesis tools are Synplicity's Synplify/Synplify Pro software and various FPGA manufacturers' own comprehensive development tools.

5. Placement and routing and implementation: Placement and routing can be understood as the use of implementation tools to map logic to the resources of the target device structure, determine the optimal layout of the logic, select the routing channel for the logic and input and output function links, and generate corresponding Files (such as configuration files and related reports); the realization is to configure the comprehensively generated logic netlist on a specific FPGA chip. Because only FPGA chip manufacturers have the best understanding of the chip structure, the layout and wiring must select the tools provided by the chip developer.

6. Programming and debugging: The final step of the design is programming and debugging. Chip programming refers to the generation of data files (Bitstream Generaon) used to load the programming data into the FPGA chip; afterwards, it can be tested on the board. Finally, download the FPGA file (such as .bit file) from the computer to the FPGA chip on the board.

6. How to use FPGA

After FPGA development is completed, the verified loading file is finally obtained. After outputting the loading file, you can start normal business processing and verification (take software loading as an example to describe the entire process)

1. Logic loading;

2. After the logic is loaded on the board software, the logic needs to be reset;

3. After the reset is completed, the software needs to wait for a period of time until the logic PLL is stable;

4. The software starts the self-check operation of the logic's external RAM, internal Block RAM, DDRC, etc.;

5. After the software completes the self-test, initialize all the writable RAM space and registers of the logic;

6. After initialization, the software refers to the configuration entry and register of the logic chip manual;

7. The logic is ready to start processing business.

7. FPGA applicable scenarios

FPGA is suitable for irregular multi-concurrency, intensive computing and protocol analysis processing scenarios, such as artificial intelligence, gene sequencing, video coding, data compression, image processing, network processing and other fields of acceleration.