Interpretation of FPGA chip SOPC transmitter circuit design

From this article you will get more information about FPGA chip SOPC transmitter circuit design, you just need to read it carefully.

This article designs an on-chip programmable system based on the FPGA chip EP3C16Q240C8N. The system can be used to implement IFFT operations and interface modules. The NiosII soft core processor that can be embedded in this FPGA chip is used to implement data transmission and control. The ADI digital upconversion chip AD9957 and the controllable gain chip AD8369 in the functional circuit are used to realize the upconversion and signal amplification of the DAB baseband signal. The size of this DAB transmitter circuit board is 100cm*160cm. After testing, it can complete the launch well and has high reliability.

DAB transmitter is an important part of digital audio broadcasting. DAB technology is one of the European Eureka projects, and it is currently very mature. DAB uses advanced digital technology, orthogonal frequency division multiplexing (OFDM), which can transmit CD quality stereo with extremely low data transmission rate and distortion The program can solve the problems of poor reception and interference of traditional analog broadcasting. The DAB transmission system includes source coding. Channel coding. Time is intertwined. Frequency interleaving. OFDM modulation and RF part. The radio frequency part includes up-conversion and gain amplification to move the baseband signal to the transmit frequency and amplify it.

FPGA technology continues to progress, while cost and power consumption continue to decline while performance and capacity are increasing substantially. FPGAs are also increasingly embedded in systems instead of MCUs. In order to facilitate system integration, the FPGA system designed in this paper is embedded in the DAB launch system, which makes development convenient and flexible, while also reducing costs.

The speed of the FPGA chip according to the configuration speed is:

Active parallel (AP) mode. Fast passive parallel (FPP) mode. AcTIve serial (AS) mode. Passive serial (PS) mode. There is also the Joint Test AcTIon Group (JTAG) mode for debugging. This article FPGA configures AS mode and JTAG mode at the same time. According to the data manual of cycloneIII, the configuration scheme is determined by the MSEL pin. When using both AS and JTAG, MSEL[3:0] is "010". Figure 2 shows the AS and JTAG configuration circuit given by ATERA. AS

The AS mode means that the EPCS controller of the FPGA sends out a signal to read the data, so that the data of the serial FLASH (EPCS series chip) is read into the FPGA to realize the programming of the FPGA. Configuration data is sent through the DATA0 pin of the FPGA, the data is synchronized on the DCLK input, and 1 bit of data is transferred in 1 clock cycle. The configuration chip EPCS16SI8 selected in this article has 16Mbits of storage space and can support DCLK clocks working at 20MHz and 40MHz. The JTAG interface is an industry standard interface, mainly used for chip testing and other functions. ALTERA FPGAs can basically support JTAG commands The way to configure the FPGA, and the JTAG configuration method has a higher priority than any other method. The JTAG mode is to store the configuration data in SRAM, and it needs to be downloaded again after power off. Its interface with FPGA consists of 4 required signals TDI, TDO, TMS and TCK and 1 optional signal TRST.