Date: Dec 18, 2020
Click Count: 741
Basic concepts of SoC FPGA
Intel Cyclone V SoC FPGA is a new SoC chip released by Intel PSG (formerly Altera) in 2013 that integrates dual-core ARM Cortex-A9 processor and FPGA logic resources on a single chip. Compared with the traditional single ARM processing Intel Cyclone V SoC FPGA not only has the flexible and efficient data operation and transaction processing capabilities of the ARM processor but also integrates the high-speed parallel processing advantages of FPGA. At the same time, based on the unique on-chip interconnection structure of the two, when using The general logic resources on the FPGA can be configured and mapped to one or more peripherals with specific functions of the ARM processor, and communicate through the AXI high-speed bus up to 128 bits wide to complete the interaction of data and control commands. Because the on-chip ARM processor is hard-wired logic that has been placed and routed, the clock frequency that it can work on is higher, and therefore more instructions can be executed per unit time.
Basic concepts of SOPC
Before the introduction of SoC FPGA technology, major FPGA manufacturers have promoted SOPC technology for many years. Unlike SoC FPGA, SOPC uses FPGA logic and memory resources to build a soft-core CPU system on a pure FPGA chip, and the soft-core CPU implements the complete functions of the required processor. Because it is a CPU built with the general logic of FPGA, it has a certain degree of flexibility. Users can customize the CPU according to their own needs and add some special functions, such as division or floating-point arithmetic units, to improve the CPU Dedicated computing performance, or delete some functions that are not used in the system to save logic resources. In addition, according to the actual needs of users, various standard or customized peripherals can be added to the CPU, such as UART, SPI, IIC, and other standard interface peripherals. At the same time, users can also use FPGA logic resources to write various special Peripherals that are then connected to the CPU bus and controlled by the CPU to realize the cooperative work of software and hardware, which increases the flexibility of the system while ensuring system performance. Moreover, if a single soft-core CPU cannot meet user needs, multiple CPU soft-cores can be added to build a multi-core system, and the multi-core CPU can work together to give the system more flexible and convenient control capabilities.
However, because the CPU is built using the general logic resources of FPGA, compared to using a hard-core processor optimized for placement and routing, the highest real clock frequency that a soft-core processor can run is lower, and it will also be corresponding Consumes more FPGA logic resources and on-chip memory resources, so the SOPC solution is only suitable for applications that do not require high overall performance of the digital processor, such as the initial configuration of the entire system, human-computer interaction, coordinated control among multiple functional modules, etc. Features.
The difference between SOPC and SoC FPGA
From an architectural point of view, SOPC and SOPC FPGA are unified, and both consist of an FPGA part and a processor part. In SoC FPGA, ARM’s Cortex-A9 hard-core processor, referred to as HPS (Hardware Processor System) is embedded, while in SOPC technology, the Nios II soft-core processor is embedded. The instruction sets of the two are different. The performance of the device is also different. Cortex-A9 hardcore processor performance is much higher than the NIOS II softcore processor.
The HPS part on the Cyclone V SoC FPGA chip not only integrates the dual-core Cortex-A9 hard-core processor, but also integrates various high-performance peripherals, such as MMU, DDR3 controller, Nand FLASH controller, etc., with these peripherals, The HPS part can run the mature Linux operating system, provide a unified system API, and reduce the developer's software development difficulty. Although the NIOS II soft-core CPU can be configured and used logic resources to build the corresponding controller to support the corresponding functions, in terms of performance and development difficulty, it is a better choice to design and develop based on the SoC FPGA architecture.
In addition, although the SoC FPGA chip contains both ARM and FPGA, the two
These are independent of each other to a certain extent. The ARM processor core on the SoC chip is not contained within the FPGA logic unit. FPGA and ARM (HPS) processors are just packaged into the same chip. The JTAG interface, power supply pins, and interface pins of the peripherals are independent. Therefore, if the SoC FPGA chip is used for design, even if the on-chip ARM processor is not used, the chip resources occupied by the ARM processor cannot be released and cannot be used as general FPGA Resources. SOPC is a CPU built using FPGA general logic and memory resources. When the CPU is not used, some of the resources occupied by the CPU can be released and reused as general FPGA resources.
To ensure a smooth and successful design process and help you turn your ideas into benefits faster, Altera provides a comprehensive design environment, including:
Quartus II development software
Mature and reliable IP library
Dual-core ARMCortex-A9MPCore processor
Nios II processor, the most versatile embedded processor in the world
Intel Cyclone V FPGA price
The prices of Cyclone V FPGAs provided by different vendors will be different, so comparisons are needed.
Intel Cyclone V FPGA development board description
Master PPGA: 5CEFA2F23C7N;
Main FPGA external clock source frequency: 50MHz
Cyclone v onboard N25Q064 SPI Flash chip, storage capacity is 8MB bytes;
Cyclone v onboard 32MB town SDRAM memory, model MT48LC16M16;
Cyclone v uses MPS's MP2315 wide-range input DC/DC to provide 3.3V power for core chip operation;
Cyclone V leads to two rows of 64p, 2.54mm pitch, which can be used for external 24Bit TET LCD screen, CY7C68013USB module, high-speed ADC acquisition module, or CMOS camera module, etc.
Cyclone v causes the 3-way button of the chip to be tested;
Cyclone v guides the chip’s 2-way LED lights for testing:
Cyclone v uses a single-row 10p, 2.54mm pitch pin header to connect to the JTAG debug port of the chip.
The actual size of the Cyclone v core board is 6.7cm x 8.4cm. The recommended default input power for the evaluation board is 1A @ 5V DC.
The Cyclone v core board provides 108 independent users 10, and the PCB traces of all users 10 are processed by differential pairs and lines of equal length.
FPGA XA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V Automotive 132-Pin CSBGA
FPGA Spartan-3 Family 50K Gates 1728 Cells 90nm Technology 1.2V Automotive 100-Pin VTQFP
CPLD XA9500XL Family 800 Gates 36 Macro Cells 64.5MHz 0.35um, CMOS Technology 3.3V Automotive 44-Pin VQFP
CPLD XA9500XL Family 1.6K Gates 72 Macro Cells 64.5MHz 0.35um Technology 3.3V 44-Pin VQFP