Implementation of IP protection based on EDA or FPGA

In recent years, the scale of a single FPGA implementation circuit has continued to expand, and designers can implement a complete system on a single FPGA

With the continuous expansion of circuit scale and the time-to-market pressure brought by competition, more and more circuit designers have begun to use well-designed and repeatedly verified circuit function modules to speed up the design process. These circuit function modules are called IP (IntellectualProperty) cores. The IP core is designed by professionals in the corresponding field and has been repeatedly verified. Owners of IP cores can make profits by selling IP. Using IP cores, designers only need to do very little design to achieve the required system. The modular design based on IP core can shorten the design cycle and improve the design quality. Field programmable gate array FPGA has programmable features, users customize circuit structure according to specific applications, so its processing speed greatly exceeds that of general-purpose processors. Compared with ASICs, FPGAs have the disadvantage that while providing flexible programming, they come at the expense of chip area, power consumption, and speed.

In recent years, the scale of a single FPGA implementation circuit has continued to expand, and designers can implement a complete system (SystemonPro-grammablbChip, SoPC for short) on a single FPGA. The emergence of the IP core provides great convenience for the design of SoPC. With the use of the IP core, the designer designs through modularization. Realize complex functions of the system easily and quickly.

When a designer purchases IP from a third party, a certain protection mechanism is needed to prevent the designer from using it in unauthorized IP cores to protect the interests of the IP core owner. At the same time, for the design completed by the designer, corresponding protection mechanisms are also needed to prevent the design from being illegally copied, stolen or tampered with. To this end, an IP core protection mechanism combining Electronic Design Automation (EDA) software and FPGA is proposed. By adding a protection mechanism in the EDA tool to prevent the designer from unauthorized use of the IP core, a protection mechanism is added in the FPGA to prevent the design from being illegally copied, stolen or tampered with.

Realize IP protection in EDA software

The design and development flow of FPGA mainly includes behavior synthesis, logic synthesis, technology mapping and place and route. In general, designers use hardware description languages (such as VHDL, Velilog) to describe circuits, and then use EDA software to process them.

In the EDA software processing flow, the behavioral synthesis converts the circuit description of the algorithm level or register transfer level (RegisterTransferLevel, referred to as RTL) into a gate-level netlist, the logic synthesis optimizes the gate-level netlist, and the technical mapping is to optimize the netlist Mapped to the specific implementation (lookup table) in FPGA, the place and route tool determines the final circuit unit position in FPGA according to certain evaluation criteria, and uses the connection resources to achieve the connection between circuit units.

If the designer uses the IP core provided by the third party to implement the required design, in order to prevent the designer from stealing the IP core, modify it, and claim it as existing, there needs to be a corresponding security mechanism to protect the IP designed by the third party nuclear.

In the processing flow of EDA software, EDA software must be able to correctly analyze the design to complete the process, so the design itself is open to EDA software. It is assumed here that the EDA software is reliable. The EDA process with IP core protection mechanism is shown in Figure 1. The IP core designed by the third party must first purchase the RTL-level IP core from the developer of the EDA software. The third party encrypts the IP core using the public key of the EDA developer and then uses the publicity provided by the designer. Key encryption. In this way, although the designer obtains the third-party IP core, he does not know the private key of the EDA software developer, so the designer cannot know the RTL-level description in the IP core.

The designer can regard the purchased IP core as a black box with known functions. After using the black box and other circuit modules to complete the circuit description, the designer imports the design into the EDA tool. The EDA tool uses the key entered by the designer and the EDA developer's key to decrypt the encrypted IP core twice to obtain a complete RTL representation of the entire design. Then, the EDA tool can conduct behavior synthesis, logic synthesis, and technology mapping on the design, and finally generate a net list after the technology mapping. It is assumed that the tools for synthesis and technology mapping are provided by an EDA developer, and the FPGA place and route tool is another EDA developer, for example, provided by the FPGA manufacturer.

Before writing the optimized gate-level netlist to a file, the EDA tool first encrypts the netlist with its own private key, and then encrypts the netlist with the public key of the layout and wiring tool provider. In this way, the designer still cannot view the netlist after synthesis and technology mapping, thereby preventing the designer from using reverse engineering to steal the IP core.

The layout and wiring tool first decrypts the encrypted netlist with its own private key, and then uses the public key of the front-end EDA tool developer to decrypt the second time, thereby obtaining the decrypted netlist. Using this netlist, the place and route tool can complete the place and route design on the chip, and finally generate a bit-stream file for FPGA configuration.