Implementation of asynchronous serial communication based on FPGA

In order to adapt to the more extensive application of fully digital automatic control, a field programmable gate array (FPGA) is used to design an asynchronous serial communication controller (UART) in a multi-module system, which makes the serial communication more integrated. Modular decomposition of the UART system structure can be divided into three modules: FPGA baud rate generator control module, FPGA data sending module and data receiving module. Use Venlog language to describe hardware functions, and use Xilinx FPGA chip to design, compile, synthesize, and download in Xilinx ISE Design Suite 13.4 environment. Use third-party simulation tool ModelSim for simulation.

Asynchronous serial communication (UART) is a widely used serial data transmission protocol. The requirements of UART are fewer transmission lines, high reliability and long transmission distance. The UART function is responsible for collecting data from the bus, converting it into a transmission format, and then sending it to the serial port. It is also responsible for receiving data from the serial port, checking and deleting additional bits, and transmitting the resulting data to the bus. Asynchronous serial communication is widely used in many fields such as military, industry, automatic control, instrumentation, communication, medicine, voice and image processing. In actual applications, special integrated chips are often used to implement UART functions, such as 8250, 8250A, 16450, 16C451, 16C551, etc. However, in practical applications, generally only a few main functions of the UART are required, and the cost of the dedicated chip is relatively large and causes a waste of resources. In recent years, with the increasing maturity of electronic design technology, especially the significant increase in the integration and speed of FPGA, a chip can be used to form a complex system. One chip can complete multi-functions such as calculation, communication and control, and the cost is greatly reduced. Based on the above considerations, this article uses FPGA to implement the UART function.

1 UART communication principle

Serial communication is divided into two types: synchronous communication and asynchronous communication. UART is a universal asynchronous serial communication transceiver. One frame of data of UART is composed of start bit, data bit, parity bit and stop bit. Data is communicated through character-by-character transmission during transmission. The transmission line is in a high state before transmission of each frame of information. When transmitting a character message, the reception of each character is synchronized by the start bit. The front of the character is a start bit. The start bit is sent low first, and the receiving side is generally notified of the transmission with a falling edge. Start, and then send the data bit after the start bit, the data bit is transmitted first low bit and then high bit, the character itself consists of 5 to 8 data bits.

After the data bit is the parity bit, and after the parity bit is the stop bit, marking the end of a frame of characters. After the stop bit is high, it is an idle bit, and prepares for the beginning of the next character transmission. When sending and receiving data, if there is a gap between the frames of the data, it is necessary to add idle bits after the stop bit, followed by the idle bits of indefinite length. The stop bit and idle bit are both specified high level, which can ensure that there is a falling edge at the beginning of the start bit. As shown in Figure 1.

1. 1 System design and hardware implementation

Asynchronous communication allows full-duplex communication on the serial link. In this paper, the asynchronous communication circuit is implemented as a whole. After receiving the data, MAX232 performs level conversion and then inputs it through the RXD end of the FPGA serial port module. After FPGA performs serial/parallel conversion, 8-bit valid data enters the bus and then enters the processing chip. After data processing, after data processing, it enters the FPGA serial port module via the bus. 8 bits of valid data are converted into serial data in parallel in the FPGA, and then output from the TXD terminal to the 12 pins of MAX232. Output.

The frame format uses 1 start bit, 8 data bits, 1 stop bit, and a baud rate of 115 200. According to the frame format used, the data to be sent is 10 bits (1 start bit, 8 data bits, 1 Bit stop bit), after sending these 10 bits, you should stop sending, and make the transmitter level at logic 1, and then wait for the next transmission.

1.2 FPGA baud rate generator module

Serial communication is RS 232/RS 485 communication, which requires that both sides of the communication have the same baud rate and other communication formats to communicate successfully. In the field of electronic communications, the baud rate (Baud Rate) refers to the modulation rate, which refers to the change in the unit time after the signal is modulated, that is, the number of changes in the carrier parameter per unit time. It is a measure of the symbol transmission rate. 1 Baud refers to the transmission of 1 symbol per second. When implementing universal asynchronous communication based on FPGA, the baud rate generator is an indispensable part. The baud rate generator is actually a frequency divider, and the baud rate dividing factor can be calculated according to the given system clock frequency and the required baud rate, and the calculated baud rate dividing factor is used as the frequency divider of the frequency divider Number to produce the desired clock frequency. In the case of setting the same baud rate for sending and receiving, the UART only needs a baud rate generator.

The clock frequency provided by the system is 10 MHz, the transmission rate of the data signal is 115 200 Hz, the clock generated by the baud rate generator samples the data signal, and the transmission data signal is set to be sampled 3 times, then the baud rate occurs The frequency generated by the device is:

3×115 200=345 600 Hz

Then the frequency division factor can be calculated according to the given system clock and the required baud rate:

1×107/345 600=28.94

It is difficult to divide the clock by 28.94, so the integer 30 is used as the dividing factor. Although this will make the clock scored 3.5% higher than the required 345 600 Hz, but such small changes will not affect the operation of the actual circuit.

1.3 FPGA data sending module

The sending process is to send the data on the parallel bus to the serial bus. The process of data transmission can be divided into idle state, loading state, sending state and sending completion state. The idle state is the idle state after the UART core is reset, waiting for the loading state. After the UART enters the idle state, when it detects that the transmission control signal is valid, it performs the loading state and starts loading the data. The loading state is that the sending module loads this frame of data to be sent into the shift register in the order of serial transmission, resets both the shift register and the counter, and makes the working clock of the shift register and the counter the system clock. When the counter reaches the upper limit of the count, it will generate an indicator signal to notify the UART core to enter the transmit state. When the UART core state machine enters the transmit state, the corresponding signal must be changed. At this time, the shift register clock must be a baud rate clock. The most important thing is to send the output signal to the RS 232 transmit port TXD. In the sending state, it also needs the control of the counter. When the counter reaches the upper limit of the count, it will generate a signal to notify the UART core to enter the sending completion state. When the UART core state machine enters the transmit state, it generates a transmit complete interrupt signal. In this way, the data can be sent from the serial port.

1.4 FPGA data receiving module

The reception of data is more complicated than the transmission of data. In the data receiving process, the receiving module of UART must first check the start bit. Generally, when the first received is low level, it marks the beginning of a data frame, but in the middle of a data frame may also include a low level bit, the system may default to this low level as the start bit , This will produce a "false start bit". Therefore, the judgment of the start bit of the data should also be included in the process of data reception. So the data receiving process can be divided into idle state, start bit detection state, data bit read state, read stop state, ready to receive and stop bit read state. After judging that the start bit is low, trigger the receiving process, enter the data bit reading state so that the serial bus input data is continuously read and stored in the register, the counter also reaches the upper limit of the count, after the reception is completed and enter Ready to complete the receiving state, the UART controller will perform parity check on the received data before outputting the result. Then enter the stop bit read state. In each state, if the enable signal is invalid, it will return to the closed state. Finally, the UART controller prepares for the next data reception and resets the signal detector in the controller.

In conclusion

This article introduces an asynchronous serial communication function based on FPGA, and adopts a multi-module method to achieve asynchronous serial communication function, which can facilitate users to cut, understand and debug according to their needs. This article uses Verilog language to design the IP core circuit of asynchronous serial parallel transceiver.

Implementing UART function with FPGA makes full use of the remaining resources of FPGA. Compared with the dedicated UART chip, it reduces the area of the system PCB board, reduces the power consumption of the system, and improves the stability of the system. In recent years, in the field of electronic design, this method of hardware software has become a popular trend. The design uses the XC3S100E in Xilinx's Spartan3E series. All communication indexes of timing simulation and hardware testing through ISE software meet the requirements, the correctness and completeness of the entire design are verified, and each function meets the expected requirements.