How to halve the power consumption of 7 series FPGA

Xilinx uses a chip manufacturing process customized for FPGAs and an innovative unified architecture to reduce the power consumption of 7 series FPGAs by more than half compared to previous generation devices.

In the process of developing the 7 series FPGA product line, Xilinx's chip architects have communicated with hundreds of customers. One topic repeatedly mentioned by customers is power consumption. Because customers have such clear requirements, Xilinx took the reduction of power consumption and power management as a priority when designing this latest generation of 28nm FPGAs that began to deliver power to customers in March this year. In fact, the power consumption of Xilinx 7 series FPGAs is only half of the previous generation devices. At the same time, the logic performance and I/O performance have been significantly improved, the transceiver performance has reached 28Gbps, and the logic capacity has reached a new high.

The key reason for the reduction in power consumption is that Xilinx chose TSMC's 28nm HPL process for 7 series FPGAs, which was developed by Xilinx and TSMC specifically for FPGAs. In addition to its many inherent advantages in power consumption, the process also has the flexibility to support power classification and voltage regulation functions, which are not available in FPGAs implemented in other processes. In addition to choosing the ideal FPGA process, Xilinx also optimized the device architecture to further reduce power consumption.

Xilinx will release an improved power analysis tool to help designers evaluate the power consumption characteristics of Xilinx FPGAs.

Top priority

Power management has undoubtedly become the most concern of most FPGA users. In the past, if a system used a normal power supply, as long as customers can plug it into a power outlet and use it normally, they will be very satisfied. When choosing an FPGA, we don’t need to pay too much attention to the power consumption of the FPGA, just Just consider the performance and capacity of the FPGA. However, things have changed.

In the past 10 years, the industry has entered a new, faster semiconductor manufacturing process era, but these processes have serious shortcomings, that is, the leakage current of transistors. At the same time, system manufacturers hope to reduce the total cost of ownership or use by providing low-power products to achieve product differentiation, and at the same time, develop a large number of innovative new products that require DC power supply (battery-powered system). Therefore, reducing power consumption and investing in power management systems is what most customers must face, even if their goal is not a handheld device. Whether you like it or not, you must pay attention to power consumption.

People-oriented power supply

At the 130nm process node, the transistors on the IC start to consume power, even if the user puts the system into "standby" or "sleep" mode. This unnecessary power consumption (often referred to as static power consumption or static leakage current) has become increasingly severe with the introduction of 90nm, 65nm and 45nm processes. In the 45nm node, the worst case, the static power consumption accounts for 30% to 60% of the general chip power consumption. The rest is the dynamic power consumption, which is the power consumed by the device when it is running the operation it is actually designed for processing. The higher the chip performance, the higher the transistor performance required, and the more serious the leakage current.

Of course, wasting electricity is not a good thing, but static power consumption also leads to a more serious result, which is the generation of heat. This heat, combined with the heat generated by the dynamic power consumption, will make the transistor leakage more serious, and in turn generate more heat. This will lead to greater leakage currents and fall into a vicious circle. If proper cooling and power consumption budgets are not taken into account, this leakage current generates heat, and the vicious cycle of heat causing more leakage currents will shorten the service life of the IC, and even cause thermal runaway, and suddenly lead to catastrophic system failure. According to extensive reports, this is a common problem with Nvidia ASIC, the core device of Microsoft's initial version of Xbox 360, which led to a large-scale recall and redesign.

Many design teams have to find ways to solve the problems caused by static power consumption. Some designers have adopted methods such as "clock and power gating" or "power islands" in their designs. Many other design teams have added heat sinks, fans, and even cooling circuits and larger power circuits to the system for cooling, so as to deal with the leakage current problem. But all these measures will increase the bill of materials cost and labor cost of the project design.

In addition to industry-wide concerns about leakage current, some companies have their own reasons for reducing power consumption. Many companies are now holding the "environmental protection banner", or simply want to differentiate their products, advertise the use of systems with lower power consumption than competing systems, which can reduce electricity costs and have a lower total cost of ownership or Operating costs. This is especially true for networks and high-performance computing, which require large, high-heat-dissipation systems to operate reliably 24/7. The power cost of these computing clusters and their cooling systems is extremely high, so if each chip can save a few watts of electricity, the sum is very impressive. Of course, any battery-powered system considers power consumption a priority, because power consumption directly affects the length of time before the battery is charged or replaced.

Although FPGAs are still widely used in commercial mobile phones (one of the few markets where sales are large enough for ASIC design), low-power applications using FPGAs have sprung up. , Which includes in-vehicle infotainment systems, driver assistance systems, soldiers’ battlefield safety communications electronics, handheld mobile medical equipment, 3D TV and movie cameras, aircraft and space explorers.

HPL process tailored for FPGA

In the process of developing the 7 series FPGAs launched last year, Xilinx evaluated a variety of 28nm foundry processes, and finally chose to cooperate with TSMC to jointly develop a process specifically for FPGAs. This new process called High Performance Low Power Consumption (HPL) uses High Dielectric Metal Gate (HKMG) technology, which can greatly reduce the leakage current of the transistor and achieve the best combination of power consumption and performance. Dave Myron, director of product management at Xilinx, said that before HPL process technology is available, Xilinx and other FPGA companies must choose between low-power (LP) and high-performance (HP) processes at a given foundry. The LP process is used for lower-performance mobile applications, while the HP process is specifically developed for high-performance graphics chips and MPUs.

Myron said: "These two processes are not ideal for FPGA. If you choose the LP process, performance is the problem, if you choose the HP process, the power consumption will exceed expectations. Although the two have room for maneuver, but they can not meet our need."

Myron continued, FPGAs have been widely used in a large number of applications, "but they still cannot fully meet the performance requirements of graphics chips and the extremely low power consumption requirements of ASICs in commercial mobile phones." Myron said that by jointly developing FPGA-specific processes , TSMC and Xilinx have found an ideal combination of transistors with both high speed and low leakage current. Myron said (see Figure 1): "With HPL, we can customize the process to be at an ideal balance between the performance and power requirements of FPGA applications. Since our devices can meet the performance-power requirements without bias, This means that customers do not have to go to the extreme of performance or power consumption, so that the design can maximize its effectiveness."

Although competitors may argue that Xilinx uses a method that does not change at 28nm, Xilinx firmly believes that the 7 series is another milestone in the history of innovation. Xilinx combined the results of various standard tests to prove that the 7 series is ideal for various applications that users are ready to implement with FPGAs.