How to check whether the FPGA pin of the JTAG port is broken?

There is a black gold AX309 board on my hand, the pin spacing of the Jtag port is 2.0mm, and the distance of the download line on my zturn board is 2.54mm, which is embarrassing for the thief. Then it was solved by welding an adapter board, but it was more troublesome. The most important thing is that the device cannot be found on the ISE. I don’t know if it’s because I’m not soldering firmly or if I plug in and plug out the live JTAG port (plugging and unplugging the live tag will damage the JTAG port pins of the FPGA chip) ).

It stands to reason that the board is now advanced, there should be protection circuits, but still be cautious.

Correct power-on sequence

1. Turn off the power of the FPGA development board;

2. Connect the JTAG emulator to the FPGA development board through the JTAG cable;

3. Insert a USB cable into the USB port of the emulator (the other end needs to be plugged into the computer)

4. Turn on the power switch on the FPGA development board

The key is to power on last.

Correct power-off sequence

1. Turn off the power of the FPGA development board;

2. Unplug the USB cable on the downloader;

3. Unplug the JTAG connection on the FPGA development board.

The key is to power off first.

How to check whether the FPGA pin of the JTAG port is broken?

Since my hands are usually cheap, I may "operate with electricity" if I don't pay attention. Once or twice may be luckily okay, but I often walk by the river with non-wet shoes, this time I am afraid it is dangerous. After excluding the problem of the download line itself, if you cannot access the JTAG port of the FPGA, it is likely that the JTAG port pin on the FPGA chip is damaged, and the inspection is also very simple. Just use a multimeter to check the TCK, TMS, TDO in the JTAG port If it is short-circuited to GND with TDI, it is grounded. If any signal is shorted to the ground signal, it means that the JTAG signal pin is damaged.

Cause Analysis

For some low-end chips, in order to save costs and simplify the design, the FPGAIO unit has no protection circuit. If powered and plugged, there will be a certain probability of static electricity and surge on the JTAG port, which will eventually lead to the breakdown of the FPGA pin (FPGA IO port If you add a diode clamp protection circuit, the problem is not much).

FPGA program writing method-AS, PS JTAG

There are three types of configuration download methods for FPGA devices:

1. Active configuration (AS)

2. Passive configuration (PS)

3.JTAG

AS mode (Active Serial configraTIon mode)

The FPGA acts as a controller each time the power is turned on. The FPGA device guides the configuration operation process. It controls the external memory and initialization process, and actively sends a read data signal to the configuration device, thus EPCS* * The data is read into FPGA to realize the programming of FPGA.

PS mode (Passive Serial configaraTIon mode)

The configuration process is controlled by an external computer or controller, and is completed by configuring devices such as enhanced configuration devices (EPC16, EPC8). EPCS is used as a control device, FPGA is used as memory, and data is written into FPGA to realize FPGA programming. This mode can realize online programming of FPGA.

JTAG mode

JTAG is directly written into the FPGA. Because it is written into the SRAM, it needs to be reprogrammed after power off. AS is programmed into the FPGA configuration chip (for example, you can write the bit to the FPGA first. Save it on the Flash on the board. After each power-on, the FPGA will automatically read and write Flash to program the FPGA).