FPGA system based on Flash and JTAG

Introduction

For situations where multiple FPGA configuration code streams need to be switched, Xilinx Company proposes a solution called System ACE, which uses CF (Compact Flash) memory card to replace the configuration PROM and a special ACE control chip to complete the CF card For reading and writing, the host computer software generates a dedicated ACE file and downloads it to the CF memory card. After power-on, it can switch between different configuration code streams through the ACE control chip.

The System ACE solution requires the purchase of a CF memory card and a dedicated ACE control chip, which increases the system construction cost and consumes more space. Moreover, the solution can only switch up to 8 configuration files. In the face of more configurations At the time of filing, this kind of solution is powerless. However, if you want to develop an alternative to System ACE, you need to choose a more appropriate reprogrammable memory, and you need to choose the appropriate transmission protocol interface to download the configuration code stream. The speed of downloading the configuration stream through the serial port or parallel port is too slow to meet the needs of rapid download in the application; downloading the configuration stream through the USB interface requires a special control chip, which increases the cost of system design.

This article selects a large-capacity NOR Flash memory to store the configuration code stream, and uses the JTAG interface to complete the FPGA multi-configuration solution for downloading the configuration code stream. Compared with the System ACE solution, this solution not only can quickly download multiple configuration streams, but also has higher configuration speed and lower implementation cost.

1 Design of JTAG interface module

In order to write the configuration code stream into the Flash memory, the host computer software is connected to the JTAG interface module through the JTAG download line. The JTAG interface module receives the JTAG signal sent by the host computer software, extracts the JTAG instruction and corresponding data from it, and generates erase and write signals for the Flash memory. According to the IEEE 1149.1-2001 standard and the characteristics of NOR Flash memory first erased and then written, the specific execution flow of designing the host computer software is shown in Figure 1. At the same time in order to complete the erasure and programming of Flash memory, this article specifies a series of custom JTAG instructions in the software design, as shown in parentheses in Figure 1. This article stipulates that the data size of one frame is 4096 bits.

After the JTAG interface module receives the JTAG signal through external pins, in order to complete the extraction of JTAG instructions and data, the JTAG interface module must include a TAP (Test Access Port) controller. The TAP controller is a 16-state state machine. The rising edge of TCK can control the state transition through the change of TMS. In a specific state, JTAG instructions and data can be stored in the instruction register (IR Instruction Register) and data register (DR Data Register). After the JTAG interface module receives the command sent by the host computer software, the corresponding explanation is listed in Table 1.

2 Flash controller and FPGA device configuration module design

2.1 Flash controller design

When programming Flash memory and using Flash memory to configure FPGA devices, you need to operate the Flash memory, so you need to design a controller module to specifically generate Flash memory control instructions. The functions to be realized by the Flash controller are: responding to the input erase, write, and read commands, and generate corresponding timing according to the commands to realize the operation of the Flash.

In order to store multiple configuration files in a piece of Flash memory, the Flash can be divided into multiple sections according to the size of the configuration file. In this way, for a specific configuration file, the scope of the input command should be within the interval where the configuration file is stored. Therefore, when erasing a certain configuration file, block erasing method should be used instead of the whole chip erasing method.

In order to write a frame configuration code stream to the Flash memory in time, the programming time of the Flash memory should be less than the waiting time after the FPGM instruction is executed. According to the calculation of the reference data in the Flash memory data manual, it is found that the time to burn a frame configuration code stream using the ordinary programming method is longer than the waiting time, and the time to burn a frame configuration code stream using the write buffer programming method is less than Waiting time, so you must choose the programming method of writing buffer to flash memory.

The command and data translation between the JTAG interface and the Flash controller is completed by the programming control module in the backward compatible JTAG controller. It will receive the erase or write commands sent by the JTAG interface, and after conversion will generate the necessary commands, addresses and data of the corresponding Flash controller. Since the data written to the Flash memory by write-once programming is less than the size of one frame configuration code stream, after receiving the write command, the programming control module will coordinate with the write command and the corresponding operation address to configure the frame configuration code stream in the buffer. Send to the Flash controller multiple times.

2.2 FPGA device configuration module design

There are four configuration modes for Virtex series FPGA devices: serial master mode, serial slave mode, parallel slave mode, and boundary scan mode. The master mode uses the internal oscillator to provide the clock, and the slave mode and boundary scan mode use the externally provided devices. clock. After the FPGA device is powered on and initialized, the configuration module sends a configuration code stream and a configuration clock to the FPGA to configure the FPGA device. Because the faster the configuration speed, the shorter the waiting time before the FPGA device works, so this scheme selects the fastest parallel slave mode [6]. Figure 2 is a timing diagram of the parallel slave mode, data (DATA[7:0]) The constraints of setup time (Tsu) and hold time (Th) must be satisfied. The FPGA device configuration module configures the FPGA device as follows:

1. The FPGA device configuration module detects that the INIT pin signal becomes high, indicating that the automatic initialization of the FPGA device has been completed after power-on, and the configuration module sends a read command to the Flash controller;

2. After receiving the configuration code stream returned by the Flash controller, the configuration module sends an 8-bit configuration code stream to the FPGA device at each rising edge of the clock;

3. The configuration module detects that the DONE pin signal becomes high, indicating that the FPGA device has been configured and the configuration process is complete.

4. Since the time from sending a read command to the Flash controller to the Flash controller returning to the configuration code stream is greater than one cycle, and the bit width of the returned data is greater than the data bit width of the parallel slave mode, the bit width of the configuration code stream must be first Convert. At the same time, in order to ensure that every rising edge of CCLK has an 8-bit configuration code stream sent out, it is also necessary to divide CCLK appropriately.

3 Design and implementation of the plan

All the control logic design of this solution is implemented with a piece of Xilinx Spartan II series XC2S200 FPGA device. Use Spansion's NOR Flash memory to store the configuration file, its model is S29GL512N, the capacity is 512 Mb. The overall block diagram of the system is shown in Figure 3. The upper computer software includes Flash programming tool and serial port tool. When programming the configuration file, the Flash programming tool transmits the JTAG command and configuration code stream to the control FPGA through the JTAG download line. At the same time, the serial port tool sends the configuration file address to the control FPGA through the serial port to complete the switching of the configuration file storage interval; when configuring the FPGA, The serial port tool sends the configuration file address and reconfiguration signal to the control FPGA through the serial port to complete the configuration file switching. If there are too many configuration files in actual application, a flash memory array can also be formed to increase the storage depth.

3.1 Designed FPGA implementation

The logic control functions realized by controlling the FPGA include communication with the host computer software iMPACT and serial port tools, flash programming and configuration of FPGA devices. Based on the modular design idea, the specific functions are decomposed into multiple modules. The functions of each module are as follows:

1. The RS232 interface module receives the configuration file address and reconfiguration signal from the serial port tool. After decoding the configuration file address, the starting address when performing various operations on the Flash memory is obtained. The reconfiguration signal is used to trigger the switch of the FPGA configuration file. .

2. JTAG module includes JTAG interface module, data cache module and programming control module. After the JTAG interface receives the JTAG instruction and data on the JTAG download line, if it is a FERASE or FPGM instruction, it sends an erase or write signal to the programming control module, if it is an FDATA0 instruction, it receives the serial data on TDI and stores the data Cache module. The data cache module is realized by using on-chip BRAM, which can store one frame of configuration code stream. After the programming control module receives the erasing signal, it generates an erasing command and operation address and sends it to the state selection module; after receiving the programming signal, it reads the configuration code stream from the data cache module, and the generated writing command and operation address are sent. To the state selection module, the operation data is sent directly to the Flash controller.

3. After the FPGA configuration module receives the start address and reconfiguration signal from the RS232 interface module, it first sends an initialization signal to the FPGA device to be configured, waits for the initialization to be completed, and continuously sends a read command and an operation address to the state selection module, and uses the slave The FPGA controller is configured with the configuration code stream returned by the flash controller.

4. The state selection module selects the input of the Flash controller according to the external programming/configuration signal, thereby deciding whether the control FPGA is currently in the state of programming the flash memory or configuring the state of the FPGA device. If it is "0", enter the command and address generated by the programming control module to control the FPGA in the flash memory state; if "1", enter the command and address generated by the configuration control module to control the FPGA to configure the FPGA device status.

The Flash controller responds to these input commands, operation addresses and data, generates the Flash memory control sequence corresponding to the commands, and returns the data output of the Flash memory.

3.2 Actual performance test

When the program is in programming mode, the system can communicate with the host computer software through the JTAG interface and serial port. After loading the appropriate configuration file, the flash memory can be erased and written. The actual writing speed is 160 Kb. .When multiple configuration files need to be programmed, send the configuration file address through the serial port tool to operate on different Flash spaces.

When in the configuration mode, the XCV1000 FPGA in the Virtex series is used as the configuration object. Its configuration file size is about 5.84 Mb. The actual configuration time is 60 ms. The calculation shows that the configuration speed is about 97 Mb/s, which is much larger than the System ACE solution. 30 Mb/s of the scheme. If you need to switch between different configuration files, send the configuration file address and reconfiguration signal from the serial port tool to achieve real-time switching of multiple configuration files.

Conclusion

This paper analyzes the advantages and disadvantages of various transmission protocol interfaces and System ACE multi-configuration solutions. According to the actual application requirements, a FPGA multi-configuration system solution based on large-capacity NOR Flash and using the JTAG interface to complete the configuration code stream download is proposed. This system uses Flash memory instead of PROM or CF card for configuration, saving hardware cost and space, and theoretically can support an unlimited number of configuration file switching, and the configuration speed of FPGA has reached more than 3 times of System ACE scheme.