Date: May 24, 2023
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Contrary to the software code, which is ultimately translated into instructions for CPU execution - given that the internal CPU circuit is fixed - the internal circuit of an FPGA (Field Programmable Gate Array) changes according to the specific hardware code written by the user.
Users can program their custom-designed circuits into the FPGA chip, which can be repeatedly modified. This adaptability renders the FPGA suitable for a variety of different application scenarios.
What is the principle that allows FPGA chips to achieve this unique feature? And what internal structure supports the repeated modifications of circuits? This article will introduce FPGA's programmable technology.
The hardware resources inside an FPGA are fixed. To simplify the understanding, the FPGA's internal structure includes fixed AND and OR gates.
According to the hardware code, when external inputs A and B are connected to the AND gate, A&B is realized, and when connected to the OR gate, A||B is achieved.
This can be understood as having two switches - by controlling the switch connected to the AND gate, AND logic is implemented, and by controlling the switch connected to the OR gate, OR logic is realized.
The structure inside the FPGA that acts like a switch is known as the programmable switch. The so-called programmable technology refers to how to form and control this programmable switch.
FPGA controls the structure of circuits through programmable switches, which can be realized using various semiconductor technologies. Historically, FPGAs have employed technologies such as fuses, anti-fuses, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), SRAM (Static Random-Access Memory), and FLASH. Modern FPGAs typically use three of these: Antifuses, FLASH, and SRAM.
Fuse connection technology is the earliest programmable technology used in Programmable Logic Devices (PLDs). Its concept is similar to that of a fuse. When a programmable device based on fuse technology is purchased, its initial state is as shown in the following diagram - all fuses are connected, and the device is unprogrammed.
By applying a high current and voltage to the input of the device, unneeded fuses can be selectively removed to realize the user's designed logic circuit. This process is the programming of the device.
For example, to implement y = a&(!b) logic, you can blow the middle two fuses in the figure.
PLDs based on fuse connection technology are called one-time programmable devices, or OTP (One Time Program), because once a fuse is blown, it cannot be restored to its original state.
Just as devices based on fuse connection technology start with connected inputs and are programmed by blowing fuses, devices based on anti-fuse connection technology start with disconnected inputs and are programmed by adding fuses.
Naturally, anti-fuses are also one-time programmable devices.
ROM (Read-Only Memory) is non-volatile, with data permanently inscribed into the ROM through a technology called a mask.
The structure of a ROM unit is shown in the following diagram. A ROM contains a large number of rows and columns. Each column has a pull-up resistor connected to logical 1, a transistor, and a potential mask connection.
Mask technology controls which transistors are connected to the corresponding columns through the mask. Because of the presence of the pull-up resistor, the original value in the column is logic 1. When one row goes into operation, the transistor connected to this row turns on, and the column with the mask connection is pulled down to logic 0. This is the process of mask programming.
Therefore, the initial value in the ROM is all 1s, and programming changes some or all of them to 0. PLDs based on ROM can only be programmed once.
PROM (Programmable Read-Only Memory) is similar to ROM. However, while ROM programming uses a fuse connection similar to that in a fuse, PROM programming uses anti-fuse blowing. Clearly, devices based on PROM are also one-time programmable devices.
Starting with EPROM (Erasable Programmable Read-Only Memory), subsequent programmable technologies no longer use fuses and antifuses, and PLDs (Programmable Logic Devices) have been upgraded from being programmable only once to being programmable multiple times. The structure of an EPROM cell is shown in the following figure.
When a row is working, the transistor is on, and the column connected to the transistor is pulled to logic 0. Programming of EPROM is done by increasing the voltage between the control gate and the drain (12V) to make the transistor fail, thus returning the column connected to it to logic 1.
Compared to standard MOS transistors, EPROM transistors have an additional polysilicon floating gate insulated by an oxide layer. The internal structure is shown in the following figure.
When the transistor is in the unprogrammed state, the floating gate is not charged and does not affect the normal operation of the control gate, i.e., the gate. When the voltage between the gate and drain is increased (12V), under the drive of the voltage, high-energy electrons pass through the oxide layer and enter the floating gate. This process is called hot electron injection.
After the programming signal is withdrawn, negative charges are stored in the floating gate. These charges are very stable and can normally be kept for more than 10 years under normal conditions.
The charge stored in the floating gate prevents the normal operation of the gate. Unprogrammed transistors normally turn on when a conduction voltage is added to the row line, and the column line is logic 0; programmed transistors cannot turn on, and the column line is logic 1. In this way, programmed units can be distinguished from unprogrammed units.
EPROM can be erased by discharging the floating gate, and the energy required for discharge is provided by a source of ultraviolet (UV) radiation. The erase time is about 20 minutes. Another potential issue is that as the manufacturing process advances, the transistors become smaller and smaller, and most of the chip surface is covered by metal. This makes it difficult for EPROM devices to absorb ultraviolet radiation, and the erase time becomes longer and longer.
The approach to programmability of EEPROM is similar to that of EPROM. EPROM programs by increasing the voltage between the gate and drain to charge the floating gate, and it returns to the unprogrammed state by discharging the floating gate through UV light exposure. EEPROM also charges the floating gate by increasing the voltage between the gate and drain.
However, it can discharge the floating gate by applying a large reverse voltage (negative pressure) between the gate and drain. The structure of an EEPROM unit is depicted in the following diagram.
The structure of an EEPROM transistor is basically the same as that of an EPROM transistor. The difference lies in the fact that the SiO2 insulating layer around the floating gate of EEPROM is very thin, which allows the electrons on the floating gate to transfer to the drain under voltage drive.
An EEPROM unit is composed of a regular MOS tube in series with an EEPROM transistor, with the addition of a control gate line and source line. The volume of an EEPROM unit is about 2.5 times that of an equivalent EPROM unit because it includes two transistors and the distance between these two transistors. Due to its size, the capacity of EEPROM is generally not large. The advantage of EEPROM is that it can be erased electrically, which is much more convenient than UV erasure.
The full name of FLASH is FLASH EEPROM, so FLASH is actually a type of EEPROM. However, for distinction, the term EEPROM generally refers to conventional EEPROM and does not include FLASH.
FLASH is also known as flash memory. The "flash" reflects that its erasure time is much faster than that of EPROM and EEPROM. This is because EEPROM erased by byte, while flash memory erased by block, thus faster.
Flash memory is divided into two types according to the writing method: NAND type and NOR type. The NAND type requires high voltage for writing, while NOR type requires high current.
The unit structure of FLASH is similar to that of EEPROM, as shown in the following diagram.
As can be seen, this unit is composed of two MOS tubes with shared floating gates and control gates.
The MOS on the left is specifically responsible for programming, erasure, and other operations.
It is a dedicated write/erase transistor, which charges/discharges the floating gate by applying positive/negative pressure between the control gate and the source of the left MOS, making the MOS on the right invalid/valid. The role of the MOS on the right is similar to the fuse in fuse connection technology, controlling whether the user signal is connected.
The principle of the unit of SRAM, or Static Random Access Memory, is shown in the following diagram. The diagram on the left illustrates the principle at the gate level, while the diagram on the right illustrates at the transistor level.
An SRAM unit consists of a pass transistor (Pass-Transistor, PT) and a flip-flop made up of two CMOS inverters. Here, PT is an NMOS tube. The SRAM unit uses the bistable state (0 and 1) of the flip-flop to record data and controls the conduction/cutoff of PT through the word line. When it's conducting, the unit outputs data, and when it's cut off, the unit outputs the original value. The SRAM unit is programmed through the word line and data.
SRAM units only use MOS tubes of ordinary structure, which allows SRAM to apply the most advanced CMOS process currently. This has also become the greatest advantage of SRAM programmable switches, a benefit which has led to most FPGAs being based on SRAM nowadays.
Additionally, SRAM is volatile memory, meaning it loses configuration information when power is disconnected. Therefore, FPGAs that employ SRAM require an attached non-volatile memory unit (usually FLASH) to store this configuration information.
The eight programmable technologies introduced earlier have been used across the entire range of Programmable Logic Devices (PLDs). As a subset of PLDs, Field Programmable Gate Arrays (FPGAs) have historically employed only four of these programmable technologies: anti-fuse, EEPROM, FLASH, and SRAM. As technology has advanced, EEPROM has been replaced by FLASH.
Therefore, modern FPGAs utilize just three programmable technologies: anti-fuse, FLASH, and SRAM. The following table summarizes the features of these three programmable technologies.
Antifuse technology offers advantages in power consumption and switch resistance, but the fact it can only be programmed once poses a significant risk. Also, the inability to use the latest CMOS process leads to lower chip integration, limiting the applications of antifuse technology.
FLASH allows repeated programming and retains its non-volatility, but reprogramming FLASH requires significant power, making it unsuitable for applications requiring frequent rewrites. In addition, the FLASH process is somewhat outdated, leading to lower integration levels.
Nowadays, FLASH is primarily used as external program storage for FPGAs rather than the main programmable component.
The main drawback of SRAM is its volatility. Other shortcomings include high standby power consumption, poor radiation tolerance, and weak security (circuit configuration information could potentially be stolen). However, the ability to employ the latest CMOS process, which implies high integration and high performance, overshadows all these weaknesses.
The majority of FPGAs in the current market are based on SRAM technology.
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