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FPGA Power System Management

Date: Dec 01, 2021

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The origins of field-programmable gate arrays (FPGAs) date back to the 1980s, evolving from programmable logic devices (PLDs). Since then, rapid improvements in FPGA resources, speed, and efficiency have made FPGAs the solution of choice for a wide range of computing and processing applications, especially when yields were not sufficient to justify the development costs of application-specific integrated circuits (ASICs). FPGAs have achieved rapid growth and are widely used in large-scale deployments. For example, following the success of using FPGAs to speed up the Bing search engine in a pilot project in 2013, Microsoft® extended the use of FPGA-equipped servers to cloud data centers.

FPGA Power System Requirements

FPGAs require several different low-voltage power supply rails, each with its own voltage and current specifications, to power their core logic, I/O circuits, auxiliary logic, transceivers, and memory. These supply rails may need to be turned on and off in a specific order to avoid damaging the FPGA. point-of-load (POL) regulators reduce the board's higher input supply voltage to the multiple input voltages required by the FPGA. Switching regulators are used as POL regulators when power conversion efficiency is critical, while linear regulators, such as low dropout (LDO) regulators, are used for noise-sensitive circuits such as PLLs and transceivers.

Typical board input voltages are 5 V, 12 V, 24 V, and 48 V, while FPGA input voltages range from less than 1 V to about 3 V. For high input voltages (12 V, 24 V, 48 V), an additional buck regulator may be required to generate the intermediate bus voltage fed to the POL regulator (see Figure 1). In the FPGA supply rail, the core voltage requires the lowest voltage (approximately equal to or below 1 V) and the highest accuracy (±3% or better) with a current level of about a few tens of amps, depending on the FPGA resource utilization. To prevent logic errors, voltage fluctuations need to be controlled to within a few tens of millivolts not only under DC conditions but also during FPGA current transients as required by FPGA supply rail tolerance specifications. The worse the DC accuracy of the power supply, the more bypass capacitance is required to maintain the available supply voltage under transient conditions. For example, assume a ±3% core voltage tolerance specification is used. When using a DC power supply with a ±1% accuracy, the corresponding transient tolerance is ±2%. With a lower accuracy of the DC supply (±2%), the transient tolerance will be tighter (±1%) and more bypass capacitance will be required compared to the previous example.

1FPGA power tree design.png

Figure 1. A possible FPGA power tree design: The high-voltage input supply (e.g., 12 V, 24 V, or 48 V) is stepped down to an intermediate bus voltage and then fed to the POL regulator powering the FPGA.

The FPGA power supply voltage level needs to be adjusted or fine tuned based on default setpoints when making eventual design changes, reusing the design in another application, implementing board margin testing, and dynamically optimizing system power consumption during development or field operation. In this case, using multiple different resistors in parallel in the power supply feedback network is not the fastest or most feasible solution. One way to implement voltage trimming is to use a digital-to-analog converter (DAC) to drive the regulator's feedback network (see Figure 2). Software code needs to be written for the trim procedure to obtain supply voltage measurements from the analog-to-digital converter (ADC) to calculate the correct DAC code, and then slowly adjust the DAC output to the calculated digital code, gradually and steadily increasing the supply voltage to reach the target voltage level without burr or overshoot. This fine-tuning procedure needs to be repeated to ensure that there are no shifts in the component over time or temperature that could cause the power supply to deviate from the target voltage.

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Figure 2. Fine-tuning the POL power supply output voltage to the target voltage using a DAC and ADC.

Monitoring FPGA supply voltages, currents, and fault conditions is critical to understanding the health and power consumption of the system in different scenarios, due to the fact that the FPGA is the heart of the entire electronic system. Combining this understanding with fine-tuning capabilities can save cost and power by avoiding designing power supplies for worst-case scenarios. In addition, potential system failures may manifest themselves as abnormal FPGA power consumption, allowing the host controller or maintenance personnel to identify problems early before a board or system failure occurs. Voltage monitoring requires the use of an ADC, while current monitoring also requires the use of level-shifting circuitry to convert high-level current detection voltages to ground reference voltages; for example, through the use of a transconductance amplifier, as shown in Figure 3.

3solution .png

Figure 3. A possible solution for discrete circuits for monitoring POL power supply output voltage, current, and power.

Although we have not yet explored fault management, you may already be dizzy after reading this long list of requirements. What happens when the POL output is undervolted or overvolted, i.e., outside of the effective voltage window? Should only the faulty power supply be turned off? Or should you shut down the other power supplies as well? How can we eliminate the faults that cause the system board to shut down?

As we can see, power system management for FPGAs can quickly become very complex, thus distracting from the basic FPGA application. Note that the FPGA power tree is only one part of the overall power system on the digital processing board. Most of the above requirements apply to other digital devices as well, such as ASICs, DSPs, GPUs, SoCs, and microprocessors. What we need is a simple, scalable and flexible power system management solution.

Digital Power System Management

ADI offers Digital Power System Management (DPSM) device products to meet the complex power system requirements in digital processing boards.DPSM devices are available with or without integrated DC/DC conversion to replace POL regulators, or for use with existing POL regulators. The power system manager does not provide DC/DC conversion, and for existing analog power systems consisting of switching or LDO regulators, digital monitoring and control functions can be added. Using a single device (e.g. LTC2980), trimming, margin adjustment, monitoring, timing control, power supply monitoring, fault logging and fault management can be implemented for 16 POL regulators. Different channel count devices (2, 4, 8 or 16 channels) can be mixed and matched to manage hundreds of supply rails. The dual-channel LTC2972 is the latest addition to this family and provides a simple entry solution to monitor and control the two most important power supply rails in such power systems; for example, the FPGA core power supply rail and the auxiliary power supply rail.

Dual-Channel Power System Manager

The LTC2972 is a dual-channel power system manager that adds comprehensive software-based monitoring, control, and black-box fault logging capabilities to FPGA, ASIC, and processor boards to speed time to market, improve system reliability, and optimize board power consumption (Figure 4). The POL power supply output voltage is trimmed, margined and monitored using an excellent 16-bit ADC with a total unadjusted error (TUE) of 0.25% to improve board power and long-term performance. Because of the ability to tightly control the POL output voltage to achieve ±0.25% accuracy, there is significant margin during load transients (±2.75% accuracy at ±3% FPGA supply rail specification), which significantly reduces the required bypass capacitance and frees up board space. The power supply output current is measured using a sense resistor, inductor DCR, or the IMON output of the power supply. The voltage and current measurements are internally multiplied to provide a POL output power reading.

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Figure 4. LTC2972 is a dual-channel power system manager that provides intermediate bus power monitoring and POL output power monitoring

The LTC2972 has built-in power timing control, monitoring, and EEPROM fault logging capabilities. Timing control is accomplished by writing time delays to internal registers or using cascaded power good signals. When the POL input voltage, output voltage and temperature digitally deviate from the upper and lower limits of the settable threshold, a dedicated fast comparator to signal a fault. Faults trigger EEPROM black-box logging, simplifying fault analysis and providing relevant insights about future system improvements. The first fault command provides additional information about the cause of the system failure. Fault information can be flexibly propagated to other power supplies or other DPSM devices.

The LTC2972 supports voltage, current, power, and power monitoring of the POL converter's intermediate bus inputs. In order to manage, optimize and reduce board power consumption, and thus reduce cooling and utility costs of servers and data centers, board power and power usage must be monitored. LTC2972 through the PMBus interface (industry standard for communication with power management and conversion devices) to easily provide output power (in joules) and runtime to reduce the heavy polling and calculation tasks. Using the LTC2972 in conjunction with the digital measurements of POL output voltage, current and power allows long-term monitoring of the conversion efficiency of power systems.

Each channel is equipped with programmable power good pins or general purpose input/output (GPIO) pins, and the LTC2972 interfaces with other power system managers for timing and fault management of more than two supply rails. Flexible programming and data readback of the power system can be implemented using compatible PMBus commands transmitted via the I2C/SMBus interface. Configuration is done in the LTpowerPlay® development environment that supports all ADI DPSM products (see Figure 5). Once the internal EEPROM is programmed with the required application-specific configuration, there is no need to write software code for automatic operation.

Figure 5. LTpowerPlay development environment for DPSM products: No need to write code for autorun.


FPGAs are used in a wide range of electronic systems, even replacing ASICs, but they are surrounded by complex power systems. If you've never used a DPSM before, you can try the LTC2972, an entry-level product that solves complex power system problems on digital processing boards. 

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