FPGA development strategies and new solutions

However, for different applications and design requirements, the development of FPGA devices is also different. On the one hand, it follows Moore's Law on high-end devices, increasing the scale of logic cells through the upgrading of manufacturing processes, and reducing the pressure of power consumption while improving performance.

The global market is picking up, and factors such as continuous siege in the ASIC and ASSP markets are driving the growth of the FPGA market. Taking the communication market as an example, based on the high flexibility of programmable devices, the amount of FPGA used in GSM equipment to LTE equipment has increased by 3.1 times in the past few years; in terms of the scale of FPGA penetration into the ASIC and ASSP markets, in 2007 Previously, programmable devices were very slow relative to the growth of the ASIC market, but after 2007 the situation changed. As of the end of last year, the total market of ASIC and ASSP was as high as 80 billion US dollars, but the growth rate has slowed down because the development costs have risen too fast. At the 90nm node, the mask cost of ASIC is about 1 million US dollars, to 65nm node, this cost rises to 2 million US dollars. Take the 28nm device price of 10-50 US dollars as an example. To cover the cost including mask, engineering design and company operation, 5 to 27 million chips must be sold. Few applications can support this amount. In contrast, FPGA, its cost advantage began to manifest after the 90nm process node. Before the 130nm node, the FPGA process has been upgraded later than the ASIC, but by 40nm, the world’s first product to use a foundry is Altera’s FPGA. At present, both Xilinx and Altera have launched 28nm FPGA samples, which exceeds the process. ASIC.

In summary, with the increasing requirements of system equipment functions, the design of system-on-chips becomes more and more complex, and faces greater challenges in terms of design cycle, flexibility, and NRE cost. This trend makes the application of FPGA devices in circuit design, product design and system design is accelerating. Due to the resources of interface, control, function IP, embedded CPU and so on, FPGA can easily realize the system product design with simple structure, high curing degree and comprehensive functions. System-level design and products are already the largest market of FPGA.

However, for different applications and design requirements, the development of FPGA devices is also different. On the one hand, it follows Moore's Law on high-end devices, increasing the size of logic cells through the upgrading of manufacturing processes, and reducing the pressure of power consumption while improving performance; on the other hand, it is low-cost, low-power and performance medium, Low-end FPGAs and CPLDs, such as devices with density ranging from 10K to 250K LUT, etc. The following will try to develop strategies, product processes and new solutions for the four most representative FPGA companies (Xilinx, Altera, Lattice and Microsemi) Make an induction.

Xilinx

Development strategy: target design platform + high performance technology

Currently, Xilinx has locked its technology development direction on the target design platform, 28Gbps serial transceiver technology, stacked silicon interconnect technology, scalable processing platform and 7 series FPGAs. There is no doubt that the target design platform is a major decision in Xilinx's development strategy and a breakthrough in its FPGA design methodology. Xilinx target design platform includes fully integrated and successfully tested software and hardware, IP and application framework, as well as applicable design environment. Its platform components include: target reference design (connection function suite, DSP suite and embedded suite), IP core and peripherals (IP core, connection function, DSP, embedded processing and Xilinx AXI4), design tools (ISE design guide , Including logic, embedded systems and DSP) and development boards and kits. In terms of specific target development, it includes a general FPGA development platform for logic design, a platform technology for specific technology areas (connectivity, DSP and embedded design), and a platform that meets industry application needs (aerospace and military, automotive, broadcast , Industry, science and medical, wireless communication and wired communication).

The 7 series on the 28nm process represents Xilinx’s latest products and technologies. The 7 series is by far the fastest product launched by Xilinx at the same time, including Artix-7, Kintex-7, Virtex-7 and the scalable processor platform Zynq, Using 28nm HPL (high performance and low power consumption) process specially developed by TSMC. Kintex-7 has 1920 DSPs, 32 12.5Gbps transceivers and 500 I/O ports. Virtex-7 has 5280 DSPs and up to 96 transceivers (including 12.5Gbps, 13.1Gbps and 28.05Gbps), while Artix-7 has 16 transceivers and built-in Agile Mixed Signal (AMS) on-chip monitoring , 12-bit 1Msps ADCs, 16 independent inputs and on-chip voltage/thermal sensor, the total power consumption is less than 1W. At present, Kintex-7 325T has begun to provide samples to customers, the first Kintex-7 development board has also been launched, AXI4 IP and target reference designs have been developed and put into operation, and ISE 13.1 design kit has been opened for 7 series design. Kintex-7 will be transferred to mass production as soon as possible in the first quarter of 2012.

The Xilinx scalable processing platform is a single-chip solution based on the ARM Cortex-A9 MPCore processor. The Zynq-7000 series is currently available. Cortex-A9 MPCore is composed of 2 CPUs, with a special NEON coprocessor (media and signal processing architecture, adding instructions for audio, video, 3D graphics, imaging and language processing) and double precision floating point unit, and Combined with low power 28nm process technology, to achieve a high degree of flexibility, powerful configuration functions and high performance. The characteristics of the Zynq-7000 scalable processing platform are: first, the software and hardware are programmable; second, the processing system is programmable at any time; third, the scalable density and performance are greatly improved (built with a cutting-edge 7 series FPGA, integrated with dual 12-bit analog-to-digital converter, speed up to 1Msps and more than 3000 internal interconnections, bandwidth up to 100Gb. Can provide up to 760 DSP engines, performance exceeds 910GMAC, can achieve massive parallel processing); Fourth, flexibility exceeds any standard Processing solutions (54 processor I/Os, 50 multi-standard and high-performance I/Os, up to 12 high-performance integrated serial transceivers and flexible memory interfaces).

Zynq-7000's product series include Zynq-7010, Zynq-7020, Zynq-7030 and Zynq-7040, Zynq-7030 and Zynq-7040 are two larger devices, both with high-speed and low-power serial connection function, Its built-in gigabit-level transceiver runs at speeds up to 10.3125 Gbps. These two products provide about 1.9 million and 3.5 million ASIC gates (ie 125,000 and 235,000 logic units) respectively, with DSP peak performances of 480 GMAC and 912 GMAC, respectively, generally aimed at high-end applications. The two smaller devices, Zynq-7010 and Zynq-7020, provide approximately 430,000 and 1.3 million ASIC gates (that is, 30,000 and 85,000 logic cells, respectively). The peak DSP performance is 58 GMAC and 158 GMAC, respectively. The low-end market. The device is expected to launch samples at the end of the year. It is said that the batch price starts at less than $15. It will exceed the dual-chip solution of ARM processor + FPGA in performance, power consumption and unit cost.

In terms of transceiver technology, Xilinx integrates 16 high-performance 28Gbps transceivers in its highest-end Virtex-7 HT FPGA, which has good jitter, anti-noise interference and crosstalk performance, and can be connected to the new generation CFP2 optical module interface. It can achieve the industry's highest bandwidth, and can provide the largest single FPGA solution for 100G-400G line cards and even more advanced new-generation communication systems.

Xilinx's Stacked Silicon Interconnect Technology (SSIT) is based on the logic architecture, block RAM, clock technology, DSP slicing, and Select I/O of 7 series FPGAs. It has been developed by TSMC. Using this technology, a single FPGA can contain 2 million logic cells, compared with 40nm FPGA, power consumption can be reduced by 50%. In a stacked silicon interconnect structure, data is routed through more than 10,000 vias on a series of adjacent FPGA chips. Compared with the need to use standard I/O connections to integrate two FPGAs on a circuit board, stacked silicon interconnect technology increases the connection bandwidth between chips with unit power consumption by 100 times, and the delay is reduced to one-fifth, and it will not Occupy any high-speed serial or parallel I/O resources. In the stacked silicon wafer interconnection technology, the passive silicon interposer is provided by TSMC. It has four conductor layers, which are the key to stack interconnection. Because the interposer is passive, there is no heat dissipation problem, which makes the ultra-large FPGA built on this technology equivalent to a single chip.

Program recommendation: broadcast video engine design platform and SMPTE2022 IP core

The platform is used to accelerate the development of high-quality video processing hardware and deliver these videos at up to 10 Gbps through Internet protocols. Based on the Virtex-6 or Spartan-6 FPGA broadcast connection kit, you can first bring video to the FPGA through the connectivity of the kit, and then create a video pipeline algorithm. Xilinx's latest broadcast products can continue to improve video quality while meeting the requirements of IP Requirements for delivering uncompressed HD, 3D, and 4K video streams on the network.

The platform consists of a broadcast-quality video and image processing IP package, a reference design that supports Virtex-6 FPGA, and a Spartan-6 FPGA broadcast connection kit, which includes Xilinx ISE design kit embedded development software. The combination of IP cores, tools, and hardware makes it easier for designers to develop real-time video processing chains for multiple broadcast application types that support various SD/HD/3D formats, frame rates, and resolutions. The FMC (FPGA Intermediate Card) connector of this kit allows designers to quickly evaluate IP video and other broadcast design (including breaking news, live events and sports reports) interfaces that require real-time performance, and integrates SD/HD/ 3G-SDI, AES3 audio, DVI, HDMI, DisplayPort, 10GbE (10 Gb Ethernet). In addition, the kit can also be used to create applications that require the highest video quality and the highest bandwidth in digital cinema and ultra-high-quality (or super HDTV) systems.

The key features of the video engine target design platform include: video and image processing IP packets, support for 1080p60, 2K, and 4K video processing, providing broadcast-quality scaling, de-interlacing, screen display, and noise reduction; SMPTE2022 IP core implementation, Full-duplex, low-jitter 3x 3G-SDI (or 6x HD-SDI) is displayed on the Virtex-6 FPGA broadcast connection kit via 10Gb Ethernet in full duplex. This system can deliver up to 6 uncompressed HD movie sources via a single link at any distance; the Inrevium Spartan-6 FPGA broadcast connection kit from Tokyo Electron Devices supports the new low-end for SD/HD/3G-SDI and AES3 audio Cost FMC and optional FMC for various display interfaces, such as HDMI, Disp layPort, and V-by-One HS; Virtex-7 HT FPGA 28 Gbps Next-generation transceiver's excellent jitter performance, support for communication and broadcast backhaul links Ultra-high aggregate bandwidth, such as EdgeQAM / CMTS applications in cable, is also very suitable for 10G-SDI standards and emerging standards to handle 4Kx2K digital cinema and ultra-high-quality 8Kx4K bandwidth; Xilinx Alliance member Vanguard Software Solutions H.264/ The AVC-I video encoder can reduce bandwidth and storage requirements without sacrificing video quality. With the help of High10 and High422 intra-frame coding features, designers can quickly and easily integrate AllianceCORE IP cores into contribution, acquisition and archiving systems, supporting SMPTE AVC-I Class50 & Class100; Kintex-7 is the industry’s first 28nm FPGA product It is very suitable for broadcast applications. The transceivers it provides can support up to 12.5 Gbps bandwidth and provide twice the performance, while the power consumption is only 50% of the previous generation FPGA.

Altera

Development strategy: embedded plan + high-performance technology

Altera started the embedded plan last year. Based on this plan, Altera has targeted four types of target markets: one is the market for integrating ARM-based processors and FPGAs into a single chip in remote communication (RU) equipment; the other is industrial control processing In the market of these devices, these processors originally used Intel or Power PC cores, and the performance was around 1500DMIPS. The third is the military market in North America and Europe. This market is similar to communication processing, mainly responsible for the processing of some data packets. The fourth is the control and processing of broadcast signals.

The Altera embedded plan includes new system-level integration tools, embedded system configuration functions, and a unified FPGA design flow. The reason for pushing Altera's embedded plan is that the power consumption bottleneck of the CPU is becoming more and more prominent. The multi-core + hardware acceleration mode has become the mainstream of system design. More and more embedded systems need to use FPGA, and FPGA support is embedded. There are more and more choices. In the face of these trends, the design needs are to provide more combinations for CPUs and configurable accelerators, reduce BOM costs, and provide more OSs for FPGA-based CPUs. Another very important support It is able to provide a unified FPGA design flow for various options.