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FPGA configuration mode

Date: Oct 18, 2022

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Although the configuration modes of FPGAs vary, the workflow of FPGAs is the same throughout the configuration process, which is divided into three parts: setup, load, and boot.

FPGA configuration mode

Although the configuration modes of FPGAs vary, the workflow of FPGAs is the same throughout the configuration process, which is divided into three parts: setup, load, and boot.

Reset ends configuration starts

There are multiple ways to bring the FPGA configuration into this process. At power-up, the FPGA's power-on reset module will keep the FPGA reset until the voltage reaches the FPGA requirements; a low pulse at the externally controlled PROG_B pin can also keep the FPGA reset.

Clear configuration memory contents

This step is called initialization, and the contents of the configuration memory are automatically cleared when the FPGA reset is completed. In this step, the FPGA I/Os are placed in the high resistance state except for the configuration-specific interface. Throughout the initialization process, the INIT_B pin is set low and restored high at the end of the initialization. If the INIT_B signal is pulled low externally, the FPGA will remain initialized. Note that the pulse width of the PROG_B signal should not be too narrow.

Sample control signal

After initialization, the INIT_B signal goes back high. The FPGA starts to acquire mode selection pin M[1:0] and variable selection pin VS. if it is active mode, the FPGA will soon give a valid CCLK. The VS signal is valid only in active BPI and its SPI mode. At this point, the FPGA starts sampling the configuration data on the rising edge of the configuration clock.


Each FPGA configuration data stream has a synchronization header, a special segment of synchronization words. The synchronization word is mainly used to help the FPGA determine the correct data location. The FPGA ignores any configuration data before the synchronization word, so the FPGA officially starts receiving configuration data only after synchronization. The synchronization word is generally composed of binary numbers with the same number of 0/1, such as AA995566 for Spartan3.

ID Check

After FPGA synchronization, the device ID in the configuration stream and the target device ID are automatically checked to see if they match. This step ensures the wrong configuration stream does not misconfigure the FPGA.

The 32-bit ID contains a 28-bit feature value and a 4-bit mask. The feature values include vendor information, device family, device size, etc. When a device ID check encounters a problem, the FPGA sets the first bit of the internal register ID_Err high, and the software also displays an error message.

Loading configuration content

After the ID check passes successfully, the FPGA starts to load the configuration data.

CRC Checksum

The FPGA will perform CRC checksum on each data frame during loading data. The FPGA will pull the INIT_B signal low and terminate the configuration process if it fails.

Startup Sequence

After the FPGA configuration data is loaded, the FPGA enters the startup sequence. The default sequence of the boot sequence events is to release the DONE pin first, activate the I/O, and start the write enable. 

In practice, the boot sequence can be set by BitGen parameters to meet different needs.

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