FPGA configuration mode

FPGA has multiple configuration modes: parallel master mode is a FPGA plus EPROM; master-slave mode can support one PROM to program multiple FPGAs; serial mode can use serial PROM to program FPGA; peripheral mode can use FPGA as a micro The peripherals of the processor are programmed by the microprocessor.

How to achieve fast timing closure, reduce power consumption and cost, optimize clock management, and reduce the complexity of FPGA and PCB parallel design has always been a key issue for system design engineers using FPGAs. Nowadays, as FPGAs move towards higher density, larger capacity, lower power consumption, and integration of more IP, system design engineers, while benefiting from these excellent performances, have to face the unprecedented performance and performance of FPGAs. New design challenges brought by the ability level.

In many project designs, Altera's Cyclone series devices based on SRAM architecture are used. Cyclone devices, like other FPGA devices, provide users with programmable resources based on gate arrays. The formation of their internal logic structure is determined by configuration data. These configuration data can be loaded into the SRAM inside the FPGA through multiple modes. Due to the volatile nature of the SRAM, the FPGA must be reconfigured each time it is powered on.

1 Cyclone FPGA configuration mode

There are three main configuration schemes for Cyclone series FPGA devices, including active serial (AS) configuration, passive serial (PS) configuration using low-cost configuration chips, and JTAG-based configuration. One of them can be used to configure the Cyclone series in practical applications. FPGA device to realize the functions that user programming needs to achieve.

Cyclone series FPGA devices are configured with SRAM cells. Because SRAM is easy to lose data after power off, the configuration data must be downloaded to the powered Cyclone device immediately. Different configuration modes can use different dedicated configuration chips or data sources

These three configuration modes are determined by the high and low levels of the mode selection pins MSEL1 and MSEL0 of the Cyclone device. If your actual application requires only a single configuration mode, you can connect the mode selection pin to the VCC terminal or the ground terminal In the process of switching pins, the operating state of the device will not be affected. In any case, before reconfiguration, you must ensure that the level of the mode selection pin is valid.

2 Active serial (AS) configuration of the configuration chip

In the AS configuration mode, new low-cost devices (such as EPCS1 and EPCS4) are used. This dedicated configuration chip is a serial configuration device with permanent memory and a four-pin simple interface. Due to its lower cost, Can solve the problem of high cost of configuration devices. The serial configuration chip provides a serial interface to access data. During configuration, the Cyclone FPGA reads data through the serial interface, if necessary, decompresses the data and configures the FPGA's SRAM cell. This mode is controlled by the FPGA to configure the interface. This scheme is called active serial configuration, or AS configuration for short. Schematic diagram of configuring a Cyclone FPGA device in AS mode

The dedicated serial configuration chip can choose EPCS1 or EPCS4. The storage space of EPCS1 is 1Mbits, and the storage space of EPCS4 is 4Mbits. The designer can choose according to the size of the configuration file. The main configuration pins of the active serial configuration chip

DCLK, serial clock input, from Cyclone FPGA device, provides serial interface clock; DATA, serial data output, read data at the falling edge of DCLK; ASDI, control signal input, latch data at the rising edge of DCLK; nCS, enable input, active low.

During system power-on, the two chips enter the power-on reset phase. Once the power-on reset is entered, the nSTATUS terminal is low and is being reset; at the same time, the CONF_DONE terminal is low and the chip has not been configured. After reset, after a delay of 100ms, the FPGA releases the nSTATUS terminal. Due to the effect of the pull-up resistor, this terminal becomes a high level and enters the configuration state. Once the reset is exited, all user I/O terminals enter a three-state state. The clock signal DCLK is generated internally by the FPGA to control the entire configuration cycle and provide the clock for the serial port circuit of the configuration chip. The frequency range of the clock signal is between 14 MHz and 20 MHz. When the falling edge of DCLK comes, the FPGA outputs the control signal and the configuration chip outputs configuration data; when the rising edge of DCLK comes, the FPGA latches the configuration data and the configuration chip latches the control signal. After all configuration data is received, the FPGA releases the CONF_DONE terminal, sets it to a high level through a 10K pull-up resistor, and begins to enter the initialization phase. Cyclone FPGA devices require 136 clock cycles to be strictly initialized. Then start to enter the user state, then the INIT_DONE pin transitions to a high level.

3 SCM-based passive serial (PS) configuration

Simplified circuit diagram of a Cyclone FPGA passive serial configuration scheme using a microprocessor. The configuration process of the single-chip microcomputer is very simple. The single-chip microcomputer only needs to use five I/O ports to connect to the FPGA. The five signal lines are: DATA0, DCLK, nCONFIG, nSTATUS, and CONF_DONE.

The specific configuration process is as follows: ①nCONFIG=0, DCLK=0, keep more than 2us; ②detect nSTATUS, if it is 0, it indicates that the FPGA has responded to the configuration request and can start configuration, otherwise an error is reported. Under normal circumstances, nSTATUS will be 0 in 1us after nCONFIG=0; ③nCONFIG=0, and wait for 5us; ④Place data on DATA0, DCLK=1, delay; ⑤DCLK=0, check nSTATUS, if it is 0, report an error and restart Start; ⑥ Prepare the next data, and repeat (4), (5) until all the data is sent; ⑦ CONF_DONE should become 1 at this time, indicating that the configuration of the FPGA has been completed. If CONF_DONE is not 1 after all data is sent out, it must be reconfigured; ⑧ After configuration is completed, several cycles of DCLK are sent out to enable the FPGA to complete initialization.

It is worth noting that the SOF or POF files generated with MAX+PlusⅡ or QuartusⅡ cannot be used directly to configure the FPGA for the microcontroller, and data conversion is required to obtain available configuration data. In MAX+PlusⅡ or QuartusⅡ, there are data conversion options. Convert the .SOF file to .rbf file, and then write the .rbf file directly to a ROM or Flash area of the microcontroller system. The starting address of this data Both the length and the length are known, just write the corresponding software according to the above process.

4 Configure data compression method

The Cyclone device is an FPGA device that supports decompression of configuration data, allowing configuration data stored in the configuration chip or other memory to be compressed data. During configuration, this compressed data is sent to the Cyclone device and immediately decompressed and SRAM Unit programming. Both AS configuration mode and PS configuration mode can support compression mode, but based on JTAG configuration mode does not support compression mode. Preliminary data shows that compression can reduce the configuration data bit stream by 35% to 60%, which can reduce the storage space and transmission speed of data and the cost of configuration equipment.

Quartus II can generate configuration files with compression, which can reduce the transmission time of the configuration chip and flash memory space and bit stream. The following uses Quartus II version 5.1 as an example to introduce two methods of compressing configuration files.

4.1 Method 1: Activate compression in the project program settings before writing the design program.

First click the Device item under the Assignments menu to pop up the SetTIngs window, then select the Cyclone device in the Family option, click the Device&Pin OpTIons pop-up window below, then select the ConfiguraTIon window and click the Generate Compressed bitstreams option, and finally press the OK key to complete the setting.

4.2 Method 2: Create a program file from the Convert Programming Files window to activate compression after the design program is written.

First pull down the File menu, click Convert Programming Files pop-up window, select the file type Programming File type (POF, SRAM HEXOUT, RBF, orTTF), then for POF output files, select the configuration device, and then select Add File to add a Cyclone SOF file, select Add the file name to the SOF Data area, click the ProperTIes option, then confirm, and finally press the Generate key to generate.

5 Conclusion

The hardware circuit of the serial configuration method is simple, the configuration process software is relatively easy to implement, and the engineering application is convenient. Cyclone series FPGA device logic resources, chip speed and other technical parameters can meet the project requirements, cost-effective, and there is a certain degree of scalability. This kind of FPGA configuration implementation method is also suitable for combination with other CPUs and other applications, as long as it strictly follows the configuration requirements of software and hardware, so it has reference value in practical applications. Today, CPLD/FPGA has become a platform for digital system development, and will move towards high integration, large capacity, low cost, low voltage, low power consumption, diversified resources, suitable for system on chip (SOC), deep submicron The process, various hard and soft IP libraries, and the practicality of dynamic reconfigurable technology have been constantly improved and improved.