FPGA circuit design skills you need know

FPGA design is different from DSP and ARM systems, compared with more flexible and free. The main purpose is to design a circuit with dedicated pins, and the connection of general-purpose I/O can be defined by itself. Therefore, there are some unique methods that can be referenced in FPGA circuit design.

1. FPGA pin compatibility design

When choosing an FPGA chip, choose a package with good compatibility as much as possible. Then, when designing the hardware circuit, it is also necessary to consider the problem of how to be compatible with multiple multi-chips. For example, EP2C8Q208C8 and EP2C5Q208 are two types of FPGAs. The chip has only a dozen I/O pin definitions that are different. On the EP2C5Q208 chip, these I/Os are general-purpose I/O pins, while on the EP2C8Q208C8 chip, they are the power and ground signals, respectively. In order to ensure that both chips can work on the same circuit board, we must connect the matching pins to the power supply and ground plane according to the provisions of EP2C5Q208. Because general-purpose I/O can be connected to power or ground signals, power or ground signals cannot be used as general-purpose I/O. In the design of the same package and compatible with multiple models of FPGA, the general standard is to design the circuit according to a chip with a small number of general-purpose I/O.

2. According to the reasonable layout of the circuit to allocate the pin function

The definition of general-purpose I/O functions of FPGA can be determined according to requirements. In the steps of the circuit diagram design, if the pin definition of the FPGA in the schematic diagram can be adjusted correspondingly according to the reasonable layout of the PCB, the later wiring work can be completed more satisfactorily. For example, the SDRAM chip is on the left of the FPGA. In the pin assignment of FPGA, the signal related to SDRAM should be assigned to the left pin of FPGA. That way, you can ensure the shortest spacing between SDRAM signals and achieve the best signal integrity.

3. FPGA preset test points

At present, the number of I/Os provided by FPGAs is increasing. In addition to the I/Os that can meet the design requirements, there are also some remaining I/Os that are not defined. These I/Os can be used as reserved test points. For example, when testing the timing of SDRAM connected to an FPGA, it is difficult to accurately measure the SDRAM related pins with an oscilloscope. And SDRAM output power is relatively high, direct and accurate measurement will introduce additional impedance, affecting the normal operation of SDRAM. If the FPGA has reserved test points, the test signal can be specified from the FPGA to the reserved test points. In this way, the waveform of this signal can be tested, and it is not easy to affect the work of SDRAM. If it is found that flying leads are necessary to solve the problem during circuit testing, these reserved test points can be used as transition points for flying leads.