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Understanding the FPGA Bitstream Structure

Date: Jan 12, 2024

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The term "bitstream" is commonly used to describe a file containing the complete internal configuration state of an FPGA, including wiring, logic resources, and IO settings. Most modern FPGAs are based on SRAM, such as the Xilinx Spartan and Virtex series. 

During power-up or subsequent FPGA reconfiguration, the bitstream is read from non-volatile storage like flash memory. It is then loaded into the internal configuration SRAM through the FPGA configuration controller.

In certain scenarios, designers need a comprehensive understanding of the internal structure of the FPGA bitstream. For instance, accessing custom low-level bitstreams using FPGA physical implementation tools, implementing complex configuration rollback schemes, generating short command sequences for FPGA reconfiguration through internal configuration ports (ICAP), and reading configuration status are some situations where this knowledge proves valuable.

Bitstream Format

The bitstream comprises the following components: padding, sync word, commands for accessing configuration registers, memory frames, and desync word.


Padding data consists of an all-zero or all-one sequence, ignored by the FPGA configuration controller. Padding data is used to separate bitstreams in non-volatile memory. Generally, using an all-one padding is convenient because the flash memory state is also all-one after erasure.

Sync Word

The sync word is a special value (0xAA995566) that notifies the FPGA configuration controller to process subsequent bitstream data.

Desync Word

The desync word informs the FPGA configuration controller of the end position of the bitstream. After the desync word, all bitstream data is ignored until the next sync word is encountered.


Commands are used to read and write FPGA configuration controller registers. Some commands appearing in each bitstream include ID-CODE, used to identify which FPGA device the bitstream belongs to. Frame address register (FAR), frame data register (FDRI), and no operation (NOOP) commands are ignored.

Memory Frames

Memory frames are the fundamental unit for configuring Xilinx FPGAs in the bitstream. The frame size depends on the specific FPGA series; different series have different frame sizes. For Virtex-6 devices, frames are 2592 bits. The number of frames varies for each Virtex-6 device, ranging from a minimum of 7491 (for LX7ST) to a maximum of 5548 (for LX550T). Frames are used for configuring multiple logic slices, IO, BRAM, and other FPGA components. Each frame has an address corresponding to the FPGA configuration space. The bitstream uses FAR and FDRI command sequences to configure frames.

The Virtex-6 FPGA Configuration User Guide contains sufficient documentation on bitstreams and commands for accessing FPGA configuration controller registers. However, detailed documentation on memory frames is not only unavailable for Xilinx FPGAs but also for FPGAs from other vendors.

Xilinx's BITGEN Utility

BITGEN is Xilinx's utility that, using the Native Circuit Description (NCD) formatted post-layout files, creates bitstreams for FPGA configuration. BITGEN is a highly configurable tool with over 100 command-line options (described in the Command Line Tools User Guide). Some options determine bitstream output format, enable compression for reduced bitstream size, enhance FPGA configuration speed, use CRC for data integrity, and enable bitstream encryption.


The following example illustrates a short bitstream configured based on differential parts. The bitstream commands are described using a script language, specifically written in Perl, and available on the accompanying website.

FPGA Bitstream Structure Example

Upon careful examination of the bitstream, it is possible to distinguish sync and desync commands, the IDCODE belonging to Virtex-6 LX240T PPGA, and two frames with 405 and 243 words, respectively.

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