FPGA-based remote control system for intelligent instruments

Abstract: In order to realize the remote control of intelligent instruments and increase the speed of the control system, the design of the remote control system of intelligent instruments is realized by using field programmable gate array (FPGA) chips and USB chips. Focus on introducing RS232 and USB interface conversion principles and FPGA programming and simulation. The system uses first-in first-out memory and finite state machine to realize the interface conversion between RS232 and USB, and realize the functions of control and data processing of the host computer. The system can greatly reduce the workload of the host computer, and can be used not only in the laboratory but also in industrial production.

At present, intelligent instruments have been widely used in scientific research and industrial production, but many instruments are scattered in different geographical locations, are not easy to operate and maintain, and have poor real-time tracking performance, large human error, and data cannot be saved. In addition, a large number of high-end instruments are quite expensive . To solve the above problems, completing the operation under the prompt of the computer can reduce the damage caused by human factors and improve the accuracy of the test data. Because the intelligent instrument is an RS232 interface and the host computer uses a USB interface, it is necessary to implement the interface conversion between RS232 and USB by the FPGA. Because FPGAs can be processed in parallel, with high integration and abundant available resources, using FPGA for data processing can reduce the workload of the host computer, reduce the time for data processing, and can also shorten the design cycle and board volume to facilitate integration. To other boards.

1 Introduction to control system and interface

1.1 System function

In the whole system, the host computer can monitor the system in real time and issue corresponding commands. The data transmitted by the intelligent instrument is transmitted to the FPGA through the RS232 interface. The FPGA judges and processes the data according to the commands issued by the host computer, and then uploads it to the host computer through the USB interface, and then the host computer displays the data processed by the FPGA , Storage and other operations.

1.2 Introduction to USB interface chip

What this design uses is EZUSBFX2 series chip CY7C68013 of CYPRESS semiconductor company. CY7C68013 is a high-performance USB 2.0 microcontroller that provides a comprehensive USB 2.0 peripheral device solution. There are three working modes: Port, Slave FIFO and GPIFMaster. This solution uses the Slave FIFO mode. In this mode, an external controller (such as an FPGA) can read/write the data buffers whose endpoints are 2, 4, 6, and 8 in FX2 like ordinary FIFOs. The function of the 8051 firmware embedded in FX2 is only to configure the registers related to the Slave FIFO, and to control when FX2 works in the Slave FIFO mode. Once the 8051 firmware configures the relevant registers and makes itself work in the Slave FIFO mode, external logic (such as FPGA) can communicate with the host at high speed according to the transmission timing of the Slave FIFO, but it is not necessary during the communication process. The participation of 8051 firmware.

1.3 Introduction to RS232 interface

The full name of the RS232C standard (protocol) is the EIARS232C standard. EIARS232C uses positive and negative voltages to represent the logic state, which is different from the TTL that the logic state is expressed by high and low levels. Therefore, in order to be able to connect with the computer interface or the TTL device of the terminal, it is necessary to transform the level and logic relationship between the EIARS232C and the TTL circuit. Discrete components and integrated circuit chips can be used to implement this transformation. The design uses the MAX3232 chip.

RS232 transmission format includes start bit (1b), valid data bit (8b), parity bit (0~2b), stop bit (1b). The transmission line is high when idle, so the start bit is low and the stop bit is high.

The parity bit can be set to odd parity, even parity, or no parity. The valid data bits are transmitted from the lower bit.

2 FPGA design

2.1 USB interface timing

In Slave FIFO mode, the connection signal of external logic and FX2 is shown in Figure 2.

In Slav e FIFO mode, the CY7C68013 chip provides full and empty flags FLAGA, FLAGB, FLAGC, FLAGD for ports 2, 4, 6, and 8. IFCLK is the clock output by FX2, which can be used as a synchronous clock for communication; SLCS is the chip select signal of FIFO; SLOE is the output enable of FIFO; SLRD is the read signal of FIFO; SLWR is the write signal of FIFO. For FPGA, 4 ports are 4 FIFOs respectively.

The FPGA detects four full-empty flag bits to read/write the corresponding FIFO respectively. FPGA can choose synchronous or asynchronous read/write, adopt asynchronous read/write in this design. When writing to the asynchronous Slave FIFO, the clock is provided by the FPGA. Data is written on each valid-invalid edge of SLWR, and the FIFO write pointer is incremented. During asynchronous Slave FIFO reading, the FIFO read pointer is incremented on each valid-invalid transition edge of SLRD to change the data.

2.2 FPGA programming

FPGA design is the core part of the whole system, which is realized by VHDL language. FPGA realizes the functions of USB and RS232 interface conversion, data processing, command transmission and so on. With the above interface timing, FPGA design can be carried out. The overall design of the FPGA part is shown in Figure 3. Module introduction:

USB and FPGA interface module: The interface conversion module between USB and FPGA, the main function is to buffer the information transmitted from the USB interface to the FPGA internal FIFO, and pass the data processed by the data processing module to the USB chip. That is, the control signal is generated to read/write the internal FIFO of the USB chip. Can be realized by reading/writing FIFO two finite state machines.

Taking reading CY7C68013 chip data as an example, according to the asynchronous read USB FIFO timing diagram can be divided into 4 states: idle state, select address state, ready to read data state, read data state, read state [6]. In the idle state, enter the select address state when the read event occurs; in the select address state, make FIFOADR[1: 0] point to OUT FIFO, enter the read data ready state; in the read data state, such as FIFO empty, wait in this state , Otherwise enter the read data state; in the read data state, make SLOE, SLRD valid, read from the data line, and then invalidate SLRD, to increment the FIFO read pointer, and then invalidate SLOE, enter the state after reading; after reading If you need to transfer more data, enter the state of preparing to read data, otherwise enter the idle state.

USB data cache module: used to cache information such as instructions sent by the computer to smart instruments. It is a first-in first-out memory FIFO generated by the IP core of the FPGA chip. The capacity is 8b*512depth. Occupies 1 block of RAM resources.

RS232 data buffer module: used to buffer data sent by intelligent instruments. It is a first-in first-out memory FIFO generated by FPGA IP core. The capacity is 8b*512depth, occupying 1 block of RAM resources.

RS232 and FPGA interface module: Interface conversion module between RS232 and FPGA. The main function is to perform serial/parallel and parallel/serial conversion.

The content cached in the USB data cache module is sent to the smart instrument through the serial port at an appropriate rate, and the data sent by the smart instrument is cached in the RS232 data cache module. This module is also implemented by two state machines. Serial communication must set the baud rate. The baud rate used here is 9600Kb/s. The clock used is 50MHz, which is equivalent to about 5028 clock cycles to transfer 1 bit of data. Here, a subtraction counter is used to control, that is, the counter counts After 5028 clock cycles, the next bit of data begins to be transferred.

Data processing module: The main function is to make corresponding processing on the data in the RS232 data buffer according to the instructions of the host computer. After processing, transfer to the upper computer. The main processing methods are timing access and smoothing. The implementation method is realized by the state machine. FPGA top-level module: mainly responsible for the flow of data between modules. And the definition of the input and output signals connected to the external chip.

When the system is working, when the collected data is uploaded to the host computer, the data channel is: the data sent by the intelligent instrument is stored in the RS232 data buffer module through the RS232 interface module for buffering. After buffering to a certain amount of data, the data processing module continuously reads the data in the FIFO and performs corresponding data processing according to the commands sent by the host computer, and then transmits the processed data to the USB interface through the USB and FPGA interface module . When the host computer issues the control command, the data channel is: the command sent by the host computer is passed to the RS232 and FPGA interface module of the FPGA through the USB port. This module determines whether it is a data processing instruction or a control instrument instruction. If it is a data processing instruction, it is passed to the data processing module for data processing as required. If it is a command to control the instrument, it will be stored in the USB data cache module, and then read by the RS232 and FPGA interface module, converted to RS2322 format and then transmitted. Because the RS232 interface is slower than the USB interface, the asynchronous clock FIFO inside the FPGA is used to solve the rate matching problem.

Buffer the data transmitted through RS232 in FIFO, and then store all the data after a certain amount of data, and then take them out continuously, so back and forth, so as to achieve continuous data collection and real-time display of the host computer. Put the data transferred via USB in another FIFO buffer, let FPGA read at the rate of RS232. This prevents data loss due to RS232 speed not keeping up with USB speed.

3 Simulation results

The system clock frequency adopted by FPGA is 50MHz, the simulation tool is Modelsim SE 6.5a, and the simulation data is continuous 8b data.

The simulation results are shown in Figure 4.

Figure 4 is the simulation result of FPGA reading USB internal FIFO. DATA is the data received from the USB port. This data already exists in the FIFO of the USB chip. FIFO DATA is the data received by FPGA. As can be seen from the above, FPGA can parse out the data received by USB.

Figure 5 shows the simulation results of the RS232 and FPGA interface. It can be seen that the serial data RXD received by RS232 has been converted to parallel data din. In the program, it is stored in the FIFO after the end of a valid byte, which can be verified by the figure. Figure 6 simulation diagram of the top module. In order to verify that the data sent by the FPGA can be received correctly, the data is sent from the FPGA first, and then sent through the TXD port of RS232, so that the RXD is connected to the TXD and then received. It is correctly received and sent to the USB interface, indicating that the timing is correct.

4 Conclusion

This article uses FPGA to realize the interface conversion and data processing between USB and RS232. The use of first-in first-out memory in the design solves the problem of data cache and rate matching. The use of finite state machine makes the program design more clear and reliable. The design concentrates complex signal operations on the FPGA and utilizes the FPGA's unique parallel processing capabilities to reduce the workload of the host computer while increasing the system's operating speed.