FPGA-based reconfigurable system and its structural analysis

The characteristics of the FPGA device that can repeatedly configure the logic multiple times make a reconfigurable system possible, making the system flexible, convenient, and reusable hardware resources.

There are two hardware and software modes for implementing electronic system functions. The general-purpose microprocessor (MPU, MCU, DSP, etc.) system based on von Neumann or Harvard architecture is a software implementation mode, and its hardware circuit structure is fixed, and functions are implemented by serial execution of instructions. The software design is flexible and easy to upgrade, but the execution speed is slow and the efficiency is low; and the application specific integrated circuit (ASIC) adopts the hardware mode to complete the function through the solidified specific operation and unit circuit. The instructions are executed in parallel, with fast execution speed and high efficiency, but the development cycle is long and lacks flexibility. In some occasions where real-time and flexibility requirements are relatively high, the effect of using a general-purpose microprocessor or ASIC is not good.

A large-scale electronic system is a combination of various logic function modules. From the perspective of the time axis, the various functional modules in the system are not working at any time, but are activated or work in turn or cyclically according to the overall requirements outside the system. As the scale of the system expands, the resource utilization rate of each functional module circuit declines instead. Therefore, system design should shift from the traditional pursuit of large-scale and high-density direction to how to improve resource utilization, and make full use of limited resources to achieve larger-scale logic design.

Reconfigurable System based on large-scale programmable device FPGA (Reconfigurable System), is to use the characteristics of FPGA can be repeatedly programmed and configured to achieve real-time circuit reconfiguration (Reconfiguration of circuitry at runtime, referred to as RCR), that is, in the electronic system Under the working state, dynamically changing the structure of the circuit is to realize the time-division multiplexing of all or part of the logic resources in the FPGA, so that the discrete logic circuit functions in time can be realized in the same FPGA sequentially.

Although the concept of reconfigurable systems has been proposed as early as 1960, there has been no major breakthrough in research in this area due to the lack of ideal reconfigurable devices. Since 1990, with the rapid development of large-scale integrated circuits, especially the emergence of large-scale programmable devices FPGA, the hardware conditions for the development of reconfigurable electronic systems have been basically equipped, and the idea of real-time circuit reconstruction has gradually caused academia Attention, which triggered a research boom on reconfigurable systems. Since 2000, FPGA-based reconstruction has received more and more attention and research in the world.

2 The basis of FPGA reconfigurable design

2.1 The structural basis of FPGA reconfigurable design

Reconfigurable design refers to the use of reusable software and hardware resources to flexibly change the design method of its own architecture according to different application requirements. The characteristics of the FPGA device that can repeatedly configure the logic multiple times make a reconfigurable system possible, making the system flexible, convenient, and reusable hardware resources.

There are two main structures of FPGA devices: one is based on anti-fuse technology, and the other is based on SRAM or FLASH programming. The anti-fuse switch is used as the basic component, which is non-volatile. After programming, the configuration data of the FPGA no longer changes and cannot be reconstructed. FPGAs based on SRAM or FLASH programming program FPGAs through SRAM or FLASH cells in the array. The SRAM unit is composed of a RAM and a PIP transistor. The RAM stores the on and off information of the PIP transistor. When the system is powered on, these information codes are written into the RAM inside the FPGA by an external circuit. After the power is turned off, the RAM Data will be lost. Therefore, SRAM or FLASH programming FPGA is volatile, and every time the power is re-powered, the FPGA must reload the data. In this way, the FPGA function system in operation can re-download new configuration data after power-off to realize different functions. This feature has become the key to the widespread application of FPGAs in many new areas, especially as a continuous driving force for the development of reconfigurable systems.

2.2 FPGA reconstruction method

According to different reconstruction methods, FPGA reconstruction can be divided into static reconstruction and dynamic reconstruction. The former refers to online programming during system idle time, that is, after disconnecting the previous circuit function, re-download the memory Different target data to change the logic function of the target system. Conventional SRAM FPGA can realize static reconstruction. The latter refers to the dynamic configuration of the FPGA chip in the real-time operation of the system (that is, changing the circuit function while still maintaining the working state of the circuit), so that all or part of the logic resources can be realized in the system at high-speed function transformation and time division multiplexing use. The dynamic reconstruction technology needs the support of a specific new FPGA based on SRAM or FLASH structure. With the relative maturity of its products and technology, the design theory and design method of dynamic reconfiguration FPGA has gradually become a new research hotspot.

According to the area of reconstruction, reconfigurable FPGA can be divided into global reconstruction and local reconstruction.

(1) Global reconfiguration

The FPGA device or system can and can only be completely reconfigured. During the configuration process, the intermediate results of the calculation must be taken out and stored in an additional storage area until all new configuration functions are downloaded. The circuits before and after reconstruction are independent of each other and have no relationship. Usually, an EPROM can be connected in series to the FPGA to store configuration data to realize the conversion of the functions before and after. The static reconstruction of conventional SRAM-based FPGAs is global reconstruction.

(2) Partial reconstruction

Reconfiguration of a part of the reconstructed device or system. During the reconstruction, the working status of the rest is not affected. This reconstruction method reduces the reconstruction range and the number of units. The reconstruction time of the FPGA is greatly shortened and it has a considerable speed advantage. The application of FPGA dynamic part reconstruction function makes the hardware design more flexible, which can be used for remote hardware upgrade, system fault tolerance and evolution hardware, and communication platform design. Dynamic partial reconfiguration can be achieved through two methods: Modular-Based Partial Reconfiguration and Module-Based Partial Reconfiguration.

Obviously, dynamic reconfiguration is superior to static reconfiguration, because static reconfiguration reconfigures the entire internal logic unit. At this time, FPGA is suspended and normal operation cannot be performed. Work can be resumed only after the reconfiguration is completed, affecting the real-time performance of the system. Dynamic reconfiguration can be fully or partially reconstructed in real time during the operation of the system without interrupting the normal logic output, so it has more flexibility and high speed.

Most FPGAs are based on the LUT lookup table structure, they are only suitable for static reconstruction, and the logic function of the FPGA is set by downloading all configuration data to the LUT at once. Depending on the FPGA's capacity and configuration, the total reconstruction time can vary from a few ms to a few seconds.

For conventional FPGAs, there are many ways to reload. In the system debugging stage, the configuration data is generally downloaded from the host through a JTAG cable. After the debugging is completed, the configuration data is generally placed in the serial PROM, and the logic is loaded into the FPGA when powered on. However, there are some faster and more flexible configuration methods for the actual operation of the system, which can shorten the FPGA reconstruction time and achieve flexible reconstruction. For example, FPGA of ALTERA can be configured in serial passive (PS) mode. The EP1K10 configuration data for a 20,000 logic gate scale is 20KB, and it can be completely reconstructed in 5ms under a 30MHz configuration clock. Although this speed is not comparable to a dynamically configured FPGA, it is also much faster than JTAG download and serial PROM configuration. Let's call it bogus dynamic restructuring. And in many systems, FPGAs are not working all the time, but perform tasks at a certain repetition rate. As long as the FPGA has time to reconfigure it in its free time, it can be considered as a dynamic configuration from a macro perspective of the system. That is real-time reconstruction.

2.3 FPGA devices supporting reconstruction

In recent years, with the development of FPGA technology, new products of FPGA devices supporting reconstruction have appeared one after another. FPGA devices of Xilinx, Altera, and Lattice are all SRAM lookup table structures. Xilinx's family of devices that support modular dynamic partial reconfiguration are the XC6200 series, 90nm process Spartan-3 and Virtex-4, Virtex-II-E and Virtex-II Pro [7]. Acmel's AT6000 series is also based on the SRAM structure, but each unit of the SRAM can access the configuration separately, that is, it supports partial reconstruction. Lattice's Flash-based FPGA stores various configuration data flows in the Flash memory and configures different logical functions after configuration. Strictly speaking, it belongs to static reconfigurable technology. Altera's Flex series, ACEX, APEX, and Cyclone series are also reconfigurable logic based on SRAM. The number of FPGA devices that support reconfiguration is gradually increasing. But the current price is relatively high. [!--empirenews.page--]

3 FPGA-based reconfigurable system structure analysis

Since the research history of reconfigurable systems is very short, no standard structure has been formed yet, so we will only do a preliminary analysis based on existing applications.

According to the granularity and method of reconstruction, reconfigurable systems can be roughly divided into two types. One is the module-level reconstruction of the coarse-grained reconstruction unit, that is, the structure of one or several sub-modules is changed during reconstruction. At this time, not only the circuit logic changes, but also the connection resources are reallocated. The circuit output configuration information required for reconstruction is generated by the compiler software in advance. Normally, the system needs to suspend work during reconstruction, and continue after the reconstruction is completed. The design of this reconfiguration system is simple, but the flexibility is insufficient, and sometimes the efficiency of hardware operations cannot be fully realized. It is more suitable for application in embedded systems.

Another type of fine-grained reconstruction unit is element-level reconstruction, that is, only the logic functions of several elements are changed during reconstruction. Normally, the allocation status of connection resources is not modified during reconstruction, and the circuit configuration information required for reconstruction is dynamically generated during the operation of the system. During reconstruction, the system can work while reconstructing. The design of this kind of reconstruction system is complex, but it has great flexibility and can fully display the efficiency of hardware operations. It is more suitable for applications such as high-speed digital filters, evolutionary calculations, and custom calculations.

From the perspective of the existing reconfigurable system organization structure, it can be distinguished according to the type of application. In the low-end applications, the general-purpose microprocessor MPU (MCU/DSP) + FPGA is mainly used; in the high-end applications, the processing is mainly used. The integrated type, that is, the resources required for system design such as processors, memory, I/O ports, LVDS, CDR, etc., are integrated into an FPGA chip to form a programmable on-chip system SoPC (System on Programmable Chip).

3.1 Structural characteristics of reconfigurable system with MPU+FPGA structure

The general-purpose microprocessor has a good interface function, which is convenient for constructing a reconfigurable system. According to the relationship between MPU and FPGA and the role they play in the system, they can be divided into two categories: the reconfigurable system where MPU controls FPGA work and the reconfigurable system where MPU works with FPGA.

3.1.1 MPU controls FPGA reconfigurable system

This kind of system uses MPU as the control core of the system, and realizes the peripheral circuit function of the controller in FPGA. In essence, this is the inheritance and development of the traditional MPU control system. According to the needs of the system, the discrete external devices and interfaces, such as SRAM, keyboard and display interface, and bus expansion, are customized in FPGA.

For example, in a multi-channel ultrasonic signal high-speed acquisition and processing system, the data stream to be processed is huge, and its processing is a computationally intensive task. Using the DSP+FPGA structure mode, FPGA is used as the DSP co-processor, and parallel computing can be performed at the speed of hardware. At the same time, its online reconfigurable feature is used to flexibly change the internal logic configuration to complete the tasks of many different algorithms.

Since the main control tasks are implemented on the MPU, the focus of the system logic implementation is on the preparation of the MPU program, while the FPGA uses more IP (Intellectual Property) cores to implement the basic function modules. Software development accounts for a larger proportion in the entire system design process Big.

3.1.2 Reconfigurable system with MPU working with FPGA

This type of system usually takes programmable logic devices as the core, and implements application-oriented logic control functions (usually implemented by state machine FSM) within it, while MPU occupies a secondary position (acting as a peripheral of the FPGA controller). It should be said that this type of system makes full use of the characteristics of programmable logic devices and MCUs to achieve complementary advantages. It is mainly used in real-time applications, parallel processing, and high-speed environments. For example, high-density FPGA is used for multi-channel A/D high-speed sampling. After being processed by the internal processing module, the results are output in parallel. The timing control of the entire process is implemented within the FPGA; while the MPU is only responsible for loading and starting the parameters of the FPGA functional modules. Peripheral tasks such as command sending and FPGA working status monitoring.

The development focus of this type of system is mainly on the hardware implementation of FPGA logic functions, and the control software of MPU is relatively simple.

In practical applications, the characteristics of the system are not as obvious as those of the above two types. There are generally systems with the above characteristics, but the proportions are different.

3.2 SoC-SoPC on a single FPGA

Combining the advantages of the system-on-chip SOC and FPGA, a new SoC that is field programmable and reconfigurable is the system-on-chip SoPC.

Taking the Altera Stratix FPGA device as an example, the Stratix system integrates hardware, software, and IP functions from a technology into a module-based design. This new architecture uses the MultiTrackTM interconnection wiring structure of CPU soft core Nios and DirectDriveTM. The Nios II series 32-bit embedded processor is a general-purpose RISC CPU, which is positioned for a wide range of embedded applications. The programmable NiosII core contains many configurable interface modules. Users can use Altera's Quartus II software and SoPC Builder tool according to design requirements, allowing designers to easily embed Nios II processors into their systems. Users can also design various hardware modules for the NiosII embedded processor through Matlab and DSP Builder, or directly use hardware description languages such as VHDL, and add them to the NiosII instruction system in the form of instructions, making it a NiosII system. The interface device is integrated with the entire on-chip embedded system instead of downloading directly into the FPGA to generate a huge hardware system. It is these important characteristics of NiosII that make