FPGA arithmetic unit can support high computing power floating point

MLP stands for Machine Learning Processing unit, which is an array of up to 32 multipliers, and an addition tree, accumulator, and rounding/saturation/normalization normalization function block. It also includes two caches, one BRAM72k and one LRAM2k, for independent or combined multiplier use.

FPGA arithmetic unit can support high computing power floating point.png

Considering the trade-off between operation energy consumption and accuracy, the most commonly used operation formats in machine learning engines are FP16 and INT8, while BF16 supported by Tensor Flow is to reduce the accuracy to obtain a larger value space. Table 1 below is the floating-point format of the maximum bit width supported by MLP, and Table 2 illustrates the respective range of values.

And this seems to be a trend in the future. Many studies have shown that floating-point or integer types with smaller bit widths can not only ensure the correct rate, but also reduce a lot of calculations. Therefore, in order to comply with this trend, MLP also supports splitting the large-bit width multiplication unit into multiple small-bit width multiplications, including integers and floating-point numbers. See Table 3 below for details.

It is worth noting that bfloat16 here is the Brain Float format, and block float is a block floating point algorithm, that is, when applying Block Float16 and lower bit wide block floating point format, the exponent bit width is unchanged, and the decimal place is reduced to less than 16bit, Therefore, the floating-point addition bit width becomes smaller, and there is no need to use a floating-point multiplication unit. Instead, integer multiplication and addition trees are sufficient. The MLP architecture can double the computing power in these formats.